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PDP-11 Unibus Design Description
Company:
Digital Equipment Corporation
Part:
Date:
1979
Keywords:
Table of Contents
Section 1
Introduction
1.1
Unibus Definition
1.2
Unibus Architecture
1.2.1
Unibus Elements
1.2.1.1
Unibus Transmission Medium
1.2.1.2
Bus Terminator
1.2.1.3
Bus Segment
1.2.1.4
Bus Repeater
1.2.1.5
Bus Master
1.2.1.6
Bus Slave
1.2.1.7
Bus Arbitrator
1.2.1.8
Processor
1.2.1.9
Interrupt Fielding Processor
1.2.2
Unibus Systems
1.2.2.1
Signal Lines
1.2.2.2
Priority Structure
1.2.2.3
Address Space
1.2.2.4
Latency
1.2.2.5
Unibus Device Arrangement
1.2.2.6
Other Unibus Device Arrangements
1.3
Protocol
1.3.1
Transaction Types
1.3.2
Priority Arbitration Transactions
1.3.3
Data Transfers
1.3.3.1
Data Transfer Definition
1.3.3.2
Data Transfer Types
1.3.3.3
Data Transfer
1.3.4
Initialization
1.4
Electrical Characteristics
Section 2
Signals
2.1
Signals and Signal Lines
2.1.1
Introduction
2.1.2
Unibus Sections
2.1.3
Unibus Signal Lines Use
2.2
Signal Transmission
2.2.1
Bus Transmission Delay
2.2.2
Skew
2.2.2.1
Skew Definition
2.2.2.2
Deskew Definition
2.2.3
Types of Unibus Signal Lines
2.2.3.1
Type-1 Line
2.2.3.2
Type-2 Line
2.2.3.3
Type-3 Line
2.3
Priority Arbitration Section
2.3.1
Non-Processor Request (NPR)
2.3.2
Non-Processor Grant (NPG)
2.3.2.1
NPG Assertion
2.3.2.2
NPG Negation
2.3.2.3
NPG Uses
2.3.3
Bus Request (BR4, BR5, BR6, BR7)
2.3.4
Bus Grant (BG4, BG5, BG6, BG7)
2.3.4.1
BG Assertion
2.3.4.2
BG Negation
2.3.5
Selection Acknowledged (SACK)
2.3.5.1
SACK Assertion
2.3.5.2
SACK Negation
2.3.6
Bus Busy (BBSY)
2.3.6.1
BBSY Assertion
2.3.6.2
BBSY Negation
2.4
Data Transfer Section
2.4.1
Data Lines (D<15:00>)
2.4.2
Address Lines (A<17:00>)
2.4.3
Control Lines (C0, C1)
2.4.3.1
Data-In Transactions
2.4.3.2
DATIP Transaction
2.4.3.3
Data-Out Transactions
2.4.4
Parity Error Indicators (PA, PB)
2.4.5
Master SYNC (MSYN)
2.4.5.1
MSYN Assertion
2.4.5.2
MSYN Negation
2.4.6
Slave SYNC (SSYN)
2.4.6.1
SSYN Assertion
2.4.6.2
SSYN Negation
2.4.7
Interrupt Request (INTR)
2.5
Initialization Section
2.5.1
Initialize (INIT)
2.5.2
AC LO
2.5.2.1
AC LO Assertion
2.5.2.2
AC LO Negation
2.5.3
DC LO
2.5.3.1
DC LO Assertion
2.5.3.2
DC LO Negation
Section 3
Protocol
3.1
Definitions and Concepts
3.1.1
Definitions
3.1.1.1
Protocol
3.1.1.2
Transaction
3.1.1.3
Bus Cycle
3.1.1.4
Multiple-Cycle Transaction
3.1.1.5
Priority Arbitration Sequence
3.1.2
Unibus Operation
3.1.3
Priority Structure
3.1.3.1
Bus Device Priority Levels
3.1.3.2
Request Lines
3.1.3.3
Interrupt Fielding Processor Priority Levels
3.1.3.4
Grants
3.1.3.5
Transmission of Grants
3.1.3.6
Cancellation of Grants
3.1.3.7
Summary
3.1.3.8
Example of Priority Arbitration
3.1.4
Note on Timing Diagrams
3.2
Priority Arbitration Transactions
3.2.1
Introduction
3.2.1.1
General Description
3.2.2
Detailed Description: Priority Arbitration Transactions
3.2.2.1
Preliminary Conditions
3.2.2.2
Detailed Description: NPR Arbitration Sequence
3.2.2.3
General Description: Interrupt Transaction
3.2.2.4
Detailed Description: BR Interrupt Arbitration Sequence
3.3
Data Transfer Transactions
3.3.1
Data-In, DATI or DATIP
3.3.1.1
General Description: Data-In Transactions
3.3.1.2
Detailed Description, DATI and DATIP
3.3.2
Data-Out, DATO or DATOB
3.3.2.1
General Description: Data-Out Transaction
3.3.2.2
Detailed Description, DATO and DATOB
3.3.3
Read/Modify/Write, DATIP-DATO/B
3.3.3.1
Description, Read/Modify/Write Transaction
3.3.4
Multiple Word Transfers
3.3.5
INTERRUPT (INTR)
3.4
Initialization Section
3.4.1
Initialization (INIT)
3.4.1.1
Processor Requirements
3.4.1.2
Arbitrator Requirements
3.4.1.3
Master/Slave Device Response
3.4.2
Power-up and Power-down Sequences
3.4.2.1
Power-up Sequence
3.4.2.2
Power-down Sequence
Section 4
Interface Design Guidelines
4.1
General
4.2
Preferred Unibus Interface Chips
4.3
Unit Load
4.4
Module PC Etch
4.5
Backplanes
4.6
Grounding
4.7
Logic Design Guidelines for Unibus Interfaces
4.8
Master Devices
4.8.1
Introduction
4.8.2
Unibus Control Logic Example
4.8.3
BR Device (One Vector)
4.8.4
BR Device (Two Vectors)
4.8.5
NPR Device
Section 5
Unibus Configuration
5.1
General
5.2
Unibus Definitions
5.2.1
Bus Segment
5.2.2
Bus Cable
5.2.3
Bus Element
5.2.4
Lumped Load
5.2.5
Bus Terminator
5.2.6
Semi-Lumped Load
5.2.7
AC Unit Load
5.2.8
DC Unit Load
5.2.9
Unibus Length and Loading
5.3
Unibus Configuration Rules
5.3.1
Maximum Cable Length (Rule No. 1)
5.3.2
Maximum DC Loading (Rule No. 2)
5.3.3
Maximum Lumped Loading (Rule No. 3)
5.3.4
Rule No. 3 Violation (Block Diagram)
5.3.5
Rule No. 3 Violation (Waveform Example)
5.3.6
Rule No. 3 Implementation (Block Diagram)
5.3.7
Rule No. 3 Implementation (Waveform Diagram)
5.3.8
Multiple Bus System (Example)
5.3.9
Skewed Cable Lengths (Rule No. 4)
5.3.10
Rule No. 4 Implementation (Example A) Block Diagram
5.3.11
Rule No. 4 Implementation (Example B) Block Diagram
5.3.12
Rule No. 4 Implementation (Waveform Example)
5.3.13
Skewed Cable Lengths, Supplement (Rule No. 5)
5.3.14
Skewed Cable Length Violation (Example)
5.3.15
Skewed Cable Length Violation (Waveform Example)
5.3.16
Violation of Rule No. 5 (Waveform Example)
5.3.17
Rule No. 5 Implementation (Waveform Example)
5.3.18
Rule Violation (Rule No. 6)
5.3.19
System Acceptance (Rule No. 7)
Appendix A
Glossary of Unibus Terms
Appendix B
Unibus Hardware
B.1
BC11A Cable
B.2
M920 Jumper
B.3
M9202 24-Inch Jumper
B.4
Terminator Cards (M930, M981)
B.5
Drivers, Receivers and Transceivers
B.6
Unibus Connector Block Pin Assignments
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