PDP-8/A Miniprocessor Users Manual

Company:Digital Equipment Corporation
Part:EK-8A002-MM-002
Date:1976-12
Keywords:
Cited by:

Table of Contents

  • Chapter 1 Introduction and Description
    • 1.1 System Description
      • 1.1.1 Central Processor Unit (CPU)
      • 1.1.2 KC8-AA Programmer's Console
      • 1.1.3 Limited Function Panel
      • 1.1.4 Memory
      • 1.1.5 MM8-A Core Memory
      • 1.1.6 MS8-A Read/Write Semiconductor Memory (RAM)
      • 1.1.7 MR8-A Read Memory (ROM)
      • 1.1.8 MR8-FB Reprogrammable Read Only Memory (PROM)
      • 1.1.9 G8016 Power Supply Regulator Module
      • 1.1.10 G8018 Power Supply Regulator Module
      • 1.1.11 Interfacing
      • 1.1.12 Option Modules
      • 1.1.13 DKC8-AA I/O Option Board (M8316)
      • 1.1.14 KM8-A Extended Option Board (M8317)
      • 1.1.15 Peripheral Options
    • 1.2 Console Operation
      • 1.2.1 Limited Function Panel
      • 1.2.2 Programmer's Console
      • 1.2.3 Entering Data From the Programmer's Console
      • 1.2.4 Examining Memory Locations
      • 1.2.5 Entering Data in Memory
  • Chapter 2 Installation and Acceptance Test
    • 2.1 Site Considerations
      • 2.1.1 Power Source
      • 2.1.2 I/O Cabling Requirements
      • 2.1.3 Fire and Safety Precautions
    • 2.2 Unpacking Instructions
    • 2.3 Packing Instructions
      • 2.3.1 BA8-C Chassis Assembly
      • 2.3.2 Other PDP-8/A Chassis Assemblies
    • 2.4 PDP-8/A Basic System Components
      • 2.4.1 Chassis Descriptions
      • 2.4.2 Expansion Techniques
      • 2.4.3 PDP-8/A Module Descriptions
        • 2.4.3.1 KK8-A Central Processor Unit (CPU)
        • 2.4.3.2 MS8-A Read/Write Random Access Memory (RAM)
        • 2.4.3.3 MR8-A Read Only Random Access Memory (ROM)
        • 2.4.3.4 MM8-AA 8K Core Memory
        • 2.4.3.5 MM8-AB 16K Core Memory
        • 2.4.3.6 DKC8-AA I/O Option Board
        • 2.4.3.7 KM8-A Extended Option Board
        • 2.4.3.8 Semiconductor Memory Power Supply
        • 2.4.3.9 Core Memory Power Supply Regulator
        • 2.4.3.10 Limited Function Panel
        • 2.4.3.11 KC8-AA Programmer's Console
    • 2.5 Installing the PDP-8/A and Turning Power On For the First Time
      • 2.5.1 Environmental and Power Requirements
      • 2.5.2 Turning on the Computer for the First Time
    • 2.6 Testing PDP-8/A Without Paper Tape Diagnostics
      • 2.6.1 Programmer's Console
      • 2.6.2 Central Processor Test Routines
      • 2.6.3 Entering Test Routines from the Programmer's Console
      • 2.6.4 Central Processor Test Routines
    • 2.7 Loading the RIM and Binary Loaders
      • 2.7.1 Loading the RIM Loader
      • 2.7.2 Checking the RIM Loader
      • 2.7.3 Loading the Binary Loader
      • 2.7.4 Loading Binary Formatted Paper Tapes
    • 2.8 Testing the PDP-8/A Using MAINDEC Diagnostic Programs
      • 2.8.1 Central Processor Unit (CPU) Test
    • 2.9 Additional Diagnostic Tests
      • 2.9.1 Memory Test
      • 2.9.2 DKC8-AA Test
      • 2.9.3 KM8-A Extended Option Board Test
      • 2.9.4 Testing Extended Memories
    • 2.10 Basic PDP-8/A Maintenance
  • Chapter 3 Interfacing to the Omnibus
    • 3.1 Omnibus Physical Description
    • 3.2 Bus Specifications
    • 3.3 Methods of Data Transfer
      • 3.3.1 Programmed I/O Transfer
      • 3.3.2 Interrupt Facility
      • 3.3.3 Data Break Transfer
      • 3.3.4 The External Bus
    • 3.4 Module Configuration on the Omnibus
    • 3.5 Omnibus Pin Assignment
    • 3.6 Major Groups of Signals
      • 3.6.1 Memory Address -- 15 Lines
      • 3.6.2 Memory Data and Memory Direction Control -- 13 Lines
        • 3.6.2.1 MD<0:11>L
        • 3.6.2.2 MD DIR L
      • 3.6.3 Data Bus -- 12 Lines
      • 3.6.4 I/O Control Signals -- 10 Lines
      • 3.6.5 DMA Control Signals -- 8 Lines
      • 3.6.6 Timing Signals -- 9 Lines
      • 3.6.7 CPU States -- 6 Lines
      • 3.6.8 Memory Timing Signals -- 5 Lines
      • 3.6.9 Miscellaneous Signals -- 18 Lines
      • 3.6.10 Special Signals
      • 3.6.11 Interconnections
    • 3.7 Detailed Description of the 96 Omnibus Signals
      • 3.7.1 Memory Address -- 15 Lines
        • 3.7.1.1 EMA<0:2>L
        • 3.7.1.2 MA<0:11>L
      • 3.7.2 Memory Data and Direction Control -- 13 Lines
        • 3.7.2.1 MD<0:11>L
        • 3.7.2.2 MD DIR L
      • 3.7.3 Data Bus -- 12 Lines
      • 3.7.4 I/O Control Signals -- 10 Lines
        • 3.7.4.1 I/O PAUSE L -- Pin CD1
        • 3.7.4.2 INTERNAL I/O L -- Pin CL1
        • 3.7.4.3 SKIP L -- Pin CS1
        • 3.7.4.4 INT RQST L -- Pin CP1
        • 3.7.4.5 C<0:2>L -- Pins CE1 (C0 L); CH1 (C1 L); CJ1 (C2 L)
        • 3.7.4.6 BUS STROBE L -- Pin CK1
        • 3.7.4.7 NOT LAST XFER L -- Pin CL1
        • 3.7.4.8 INITIALIZE H -- Pin CR1
      • 3.7.5 DMA Control Signals -- 8 Lines
        • 3.7.5.1 BRK IN PROG L -- Pin BE2
        • 3.7.5.2 CPMA DISABLE L -- Pin CU1
        • 3.7.5.3 MS, IR DISABLE L -- Pin CV1
        • 3.7.5.4 MA, MS LOAD CONT L -- Pin BH2
        • 3.7.5.5 BREAK DATA CONT L -- Pin BK2
        • 3.7.5.6 OVERFLOW L -- Pin BJ2
        • 3.7.5.7 BK CYCLE L -- Pin BL2
        • 3.7.5.8 RUN L -- Pin BU2
      • 3.7.6 Timing Signals -- 9 Lines
      • 3.7.7 CPU STATE -- 6 Lines
        • 3.7.7.1 Major State Lines
        • 3.7.7.2 IR<0:2>L
      • 3.7.8 Memory Timing Signals -- 5 Lines
        • 3.7.8.1 SOURCE H -- Pin AL2, and RETURN H -- Pin AR2
        • 3.7.8.2 WRITE H -- Pin AS2
        • 3.7.8.3 INHIBIT H -- Pin AP2
        • 3.7.8.4 STROBE H -- Pin AM2
      • 3.7.9 Miscellaneous Signals -- 18 Lines
        • 3.7.9.1 IND1 L -- Pin CU2, and IND2 L -- Pin CV2
        • 3.7.9.2 MEM START L -- Pin AJ2
        • 3.7.9.3 STOP L -- Pin DS2
        • 3.7.9.4 LINK L -- Pin AV2
        • 3.7.9.5 LINK LOAD L -- Pin CS2, and LINK DATA L -- Pin CR2
        • 3.7.9.6 F SET L -- Pin DP2
        • 3.7.9.7 USER MODE L -- Pin DM2
        • 3.7.9.8 INT IN PROG H -- Pin BP2
        • 3.7.9.9 LA ENABLE L -- Pin BM2, and KEY CONTROL L -- Pin DU2
        • 3.7.9.10 PULSE LA H -- Pin DR2
        • 3.7.9.11 ROM ADDRESS L -- Pin AU2
        • 3.7.9.12 NTS STALL L -- Pin BR2
        • 3.7.9.13 SW -- Pin DV2
        • 3.7.9.14 POWER OK H -- Pin BV2
        • 3.7.9.15 RES -- Pin BS2
        • 3.7.9.16 Special Signals
    • 3.8 Timing
      • 3.8.1 Time Pulses and Time States
      • 3.8.2 Memory Timing
      • 3.8.3 Relationships Between CPU and Memory Timing
      • 3.8.4 Basic I/O Timing
      • 3.8.5 Expanded I/O Timing
      • 3.8.6 Data Break Timing
        • 3.8.6.1 Data Exchange
        • 3.8.6.2 Final Operations
      • 3.8.7 CPU Major States
        • 3.8.7.1 IR (FETCH Cycle)
        • 3.8.7.2 Interrupt Recognition
      • 3.8.8 Timing Start and Stop
    • 3.9 Asynchronous Signals
    • 3.10 Special Signals
    • 3.11 Electrical Characteristics and Interfacing
      • 3.11.1 Logic Levels
      • 3.11.2 Bus Loads
      • 3.11.3 Driving the Omnibus
    • 3.12 Drive Available for Peripherals
    • 3.13 Receivers and Load Relief Techniques
    • 3.14 Interface Examples
      • 3.14.1 Programmed I/O Interface Example
      • 3.14.2 Flag Logic
      • 3.14.3 Interrupt Request
      • 3.14.4 Output Buffer
      • 3.14.5 Input Buffer
      • 3.14.6 I/O Control
      • 3.14.7 Input/Output Timing for Programmed I/O Interfaces
    • 3.15 Program Interrupt Transfers
      • 3.15.1 Interrupt Timing
      • 3.15.2 Data Break Interface Example
      • 3.15.3 Data Break Timing
    • 3.16 Three-Cycle Data Break
    • 3.17 General Cautions Regarding Interface Design
    • 3.18 Transmission Line Effects
    • 3.19 External Bus
      • 3.19.1 Positive I/O Bus Interfacing
      • 3.19.2 The Nature of the External Bus
      • 3.19.3 External Bus Signals
      • 3.19.4 External Bus Signals
        • 3.19.4.1 BAC 00-11
        • 3.19.4.2 AC 00-11
        • 3.19.4.3 BMB 00-11
        • 3.19.4.4 BIOP 1, 2, and 4
        • 3.19.4.5 BTS1, BTS3
        • 3.19.4.6 B RUN
        • 3.19.4.7 AC CLEAR
        • 3.19.4.8 SKIP
        • 3.19.4.9 B INITIALIZE 1
        • 3.19.4.10 DATA 00-11
        • 3.19.4.11 B BREAK
        • 3.19.4.12 DATA OUT
        • 3.19.4.13 DATA ADD 00-11
        • 3.19.4.14 BRK RQST
        • 3.19.4.15 ADD ACCEPTED
        • 3.19.4.16 MB INCREMENT
        • 3.19.4.17 CA INCREMENT INH
        • 3.19.4.18 3 CYCLE
        • 3.19.4.19 WC OVERFLOW
        • 3.19.4.20 EXT DATA ADD 0-2
        • 3.19.4.21 B INITIALIZE 2
  • Chapter 4 Central Processor Unit
    • 4.1 Central Processor Unit, General Description
    • 4.2 Timing Generator
      • 4.2.1 Power On/Run Logic
      • 4.2.2 Timing Register Logic
      • 4.2.3 CPU Timing Logic
      • 4.2.4 Memory Timing Logic
      • 4.2.5 I/O Transfer Stall Logic
      • 4.2.6 Memory Stall Logic
    • 4.3 Front Panel Operations
      • 4.3.1 Limited Function Panel
      • 4.3.2 Programmer's Console
        • 4.3.2.1 Clock Timing Logic
        • 4.3.2.2 Register Logic
        • 4.3.2.3 Multiplexer Logic
        • 4.3.2.4 Register/Multiplexer Gating Logic Timing
        • 4.3.2.5 ADDRS/DISP Readout Circuit Logic
        • 4.3.2.6 Function Button Logic
        • 4.3.2.7 DISP Button Logic
        • 4.3.2.8 THIS, HLT, BOOT Logic
        • 4.3.2.9 Console Control Logic
    • 4.4 Instruction Decoder
      • 4.4.1 Instruction Register Logic
      • 4.4.2 Major State Register Logic
      • 4.4.3 DATA ENA/DATA CMP Logic
      • 4.4.4 Address Update Logic
      • 4.4.5 Major Register Load Signal Logic
      • 4.4.6 AC Register Control Logic
    • 4.5 Major Register Gating
      • 4.5.1 Page Logic
      • 4.5.2 Carry In Logic
      • 4.5.3 Skip Logic
      • 4.5.4 Link Logic
    • 4.6 I/O Transfer Logic
      • 4.6.1 Programmed I/O Transfer Logic
      • 4.6.2 Processor IOT Logic
      • 4.6.3 Program Interrupt Logic
      • 4.6.4 Data Break Transfers
  • Chapter 5 Memory Options
    • Section 1 MR8-A Read Only Memory (ROM)
    • 5.1 MR8-A Read Only Memory (ROM) Description
      • 5.1.1 MR8-A Physical Description
      • 5.1.2 MR8-A Specifications
    • 5.2 Functional Description
      • 5.2.1 Addressing
      • 5.2.2 Timing and Control
      • 5.2.3 Input and Output Signal Definition
    • 5.3 Programming
      • 5.3.1 Programming Operation
      • 5.3.2 Programming Procedure
        • 5.3.2.1 Preparation of the Paper Tape
        • 5.3.2.2 Blasting
    • 5.4 Detailed Logic Description
      • 5.4.1 Addressing Block Diagram Description
      • 5.4.2 Field and Size Selection
      • 5.4.3 Chip Select Decoder
      • 5.4.4 The 13th Bit
      • 5.4.5 Timing and Control
      • 5.4.6 Timing Generation
        • 5.4.6.1 Control Flip-Flops
        • 5.4.6.2 Sequence of Control Operations
        • 5.4.6.3 Initial Conditions
        • 5.4.6.4 Single Stepping
      • 5.4.7 Memory Data and Memory Register
        • 5.4.7.1 Memory Chips
        • 5.4.7.2 Address and Chip Enable Inputs
        • 5.4.7.3 Memory Output Register
        • 5.4.7.4 Data Transfer Lines
        • 5.4.7.5 Physical Layout
    • 5.5 MR8-A Switch List
    • Section 2 Random Access Memory (RAM)
    • 5.6 Semiconductor Random Access Memory (RAM-MS8-A) Description
      • 5.6.1 Physical Description
      • 5.6.2 MS8-A Specifications
    • 5.7 Functional Description
      • 5.7.1 Address Select Logic
      • 5.7.2 Timing and Control
      • 5.7.3 Memory Chip Array
      • 5.7.4 Memory Data
      • 5.7.5 Operation
    • 5.8 Input and Output Signals
    • 5.9 Programming
      • 5.10 Detailed Logic Description
        • 5.10.1 Address Selection Logic
        • 5.10.2 Field Selection
        • 5.10.3 Starting Address
        • 5.10.4 Memory Size Selection
    • 5.11 Timing and Control Logic
      • 5.11.1 MS8-A Timing Chain
      • 5.11.2 Operation of a RAM Cycle
        • 5.11.2.1 Read Cycle
        • 5.11.2.2 Write Cycle
      • 5.11.3 Operation of a ROM-RAM Cycle
      • 5.11.4 Memory Data and Memory Output Register
    • 5.12 Switch Definitions
    • Section 3 MR8-FB Reprogrammable Read Only Memory (PROM)
    • 5.13 MR8-FB 1K Memory
      • 5.13.1 MR8-FB Specifications
      • 5.13.2 MR8-FB Description
      • 5.13.3 Address Decoder
      • 5.13.4 Starting Address Decoder
      • 5.13.5 Bootstrap Operation
      • 5.13.6 Memory Control and Timing Logic
      • 5.13.7 Read or Read/Write
      • 5.13.8 1K PROM
      • 5.13.9 13th Bit PROM
      • 5.13.10 ROM Address Flag
      • 5.13.11 Read/Write Memory (RAM)
      • 5.13.12 Data Multiplexer
    • 5.14 MR8-FB Programming
    • 5.15 Detailed Logic Description
      • 5.15.1 Address Decoder
      • 5.15.2 Timing and Processor Control for SW Start of Memory
      • 5.15.3 Field and Starting Address Select Logic
      • 5.15.4 Memory Address Control Signal Generation
      • 5.15.5 NTS STALL
      • 5.15.6 ROM ADDR
      • 5.15.7 1K PROM Memory and Control Logic
      • 5.15.8 256 Read/Write Memory and Control Logic
      • 5.15.9 ROM and RAM Data Multiplexer
    • 5.16 Maintenance
    • Section 4 Core Memory Systems
    • 5.17 Memory System, General Description
    • 5.18 Memory System, Functional Description
    • 5.19 MM8-AA 8K Core Memory System
      • 5.19.1 Memory Core
      • 5.19.2 Hysteresis Loop
      • 5.19.3 X/Y Select Lines
      • 5.19.4 Read Operations
      • 5.19.5 Write Operations
      • 5.19.6 Magnetic Core In Two-Dimension Array
      • 5.19.7 Assembly Of 12-Stacked Core Mats
      • 5.19.8 Core Selection System
      • 5.19.9 Organization Of X/Y Drivers and Current Source
      • 5.19.10 X and Y Current Sources -- General Description
      • 5.19.11 Stack Charge Circuit
      • 5.19.12 Power Fail Circuit
      • 5.19.13 Core Selection Decoders
      • 5.19.14 Address Decoding Scheme
      • 5.19.15 Diode Selection Matrix
      • 5.19.16 Operation of Selection Switches
      • 5.19.17 Operation of the Core Selection Switches
      • 5.19.18 Sense/Inhibit Function
      • 5.19.19 Sense/Inhibit Line
      • 5.19.20 Read/Write Operation
      • 5.19.21 Inhibit Control Logic
      • 5.19.22 Field Select Control Logic
      • 5.19.23 Sense Register Enable Logic
      • 5.19.24 Sense Register Clear Timing
      • 5.19.25 Strobe Control Logic
      • 5.19.26 Strobe Setting Jumpers
      • 5.19.27 Sense Amplifiers
      • 5.19.28 Sense Register
      • 5.19.29 Inhibit Driver Load Gates
      • 5.19.30 Inhibit Drivers
      • 5.19.31 Current Source
      • 5.19.32 POWER NOT OK
      • 5.19.33 Test Points
      • 5.19.34 Circuit Variables
      • 5.19.35 Core Memory Troubleshooting
    • 5.20 MM8-AB 16K Core Memory System
      • 5.20.1 Assembly of Twelve Core Mats
      • 5.20.2 Address Decoding Scheme
      • 5.20.3 Operation of the Core Selection Switches
      • 5.20.4 Read/Write Operation
      • 5.20.5 Field Select Control Logic
      • 5.20.6 Inhibit Control Logic
      • 5.20.7 Sense Register Enable Logic
      • 5.20.8 Sense Register Clear Timing
      • 5.20.9 Strobe Control Logic
      • 5.20.10 Strobe Setting Jumpers
      • 5.20.11 Inhibit Driver Load Gates
      • 5.20.12 Sense Amplifier
      • 5.20.13 Inhibit Drivers
      • 5.20.14 Current Source
      • 5.20.15 POWER OK
      • 5.20.16 Test Points
  • Chapter 6 PDP-8/A Option Modules
    • Section 1 DKC8-AA I/O Option Module (M8316)
    • 6.1 DKC8-AA I/O Option Module Block Diagram Description
      • 6.1.1 Serial Line Unit (SLU)
      • 6.1.2 General Purpose 12-Bit Parallel I/O
      • 6.1.3 Real Time Crystal Clock
      • 6.1.4 Front Panel Control
    • 6.2 Serial Line Unit
      • 6.2.1 SLU Specifications
    • 6.3 SLU Functional Description
      • 6.3.1 Methods of Data Transfer
      • 6.3.2 Transmit Operation
      • 6.3.3 Receive Operation
      • 6.3.4 SLU Timing Generator
      • 6.3.5 Parity Generation
      • 6.3.6 Number of Bits Per Character
    • 6.4 SLU Programming
    • 6.5 SLU Detailed Logic Description
      • 6.5.1 Device Select Logic
      • 6.5.2 SLU Operation Decoder
      • 6.5.3 SLU Interrupt and Skip Logic
      • 6.5.4 SLU Timing Generator and Baud Rate Select Logic
      • 6.5.5 Universal Asynchronous Receiver/Transmitter (UART)
        • 6.5.5.1 UART Receive Operation
        • 6.5.5.2 UART Transmit Operation
      • 6.5.6 Level Converters
      • 6.5.7 Reader Run Logic
      • 6.5.8 Request to Send and Terminal Ready
    • 6.6 Real Time Clock
    • 6.7 Real Time Clock Programming
    • 6.8 Real Time Clock Detailed Logic Description
      • 6.8.1 Device Select and Operation Decoder Logic
      • 6.8.2 Real Time Clock Frequency Dividers
      • 6.8.3 Real Time Clock Interrupt and Skip Logic
    • 6.9 General Purpose Parallel I/O Block Diagram Description
    • 6.10 General Purpose Parallel I/O Programming
    • 6.11 Detailed Logic Description
      • 6.11.1 Device Select and Operations Decoder
      • 6.11.2 Interrupt and Skip Logic
      • 6.11.3 Receive and Transmit Operations
        • 6.11.3.1 Transmit Operation
        • 6.11.3.2 Receive Operation
      • 6.11.4 Strobe
      • 6.11.5 Parallel I/O Output Register
      • 6.11.6 Parallel I/O Input Buffer and Data Gates
    • Section 2 KM8-A Extended Option Module (M8317)
    • 6.12 KM8-A Extended Option Board (M8317)
      • 6.12.1 Memory Extension
      • 6.12.2 Timeshare Option
      • 6.12.3 Power Fail/Auto Restart
      • 6.12.4 Bootstrap Loader
    • 6.13 Memory Extension and Timeshare Description
    • 6.14 Memory Extension Block Diagram Description
      • 6.14.1 Control Logic
      • 6.14.2 Instruction Field Register (IF)
      • 6.14.3 Data Field Register (DF)
      • 6.14.4 Instruction Buffer Register (IB)
      • 6.14.5 Save Field Register (SF)
    • 6.15 Timeshare Control Block Diagram Description
    • 6.16 Memory Extension and Timeshare Programming
      • 6.16.1 Memory Extension Programming
      • 6.16.2 Timeshare Programming
    • 6.17 Memory Extension and Timeshare Detailed Logic Description
      • 6.17.1 Memory Extension/Timeshare Device Select
      • 6.17.2 Memory Extension and Timeshare Operation Decoder
      • 6.17.3 Input Multiplexer
      • 6.17.4 Instruction Field Register and Controls
      • 6.17.5 Data Field Register and Controls
      • 6.17.6 Output Multiplexer
      • 6.17.7 Timeshare User Buffer Register and Control Logic
      • 6.17.8 Trap Detect Logic
      • 6.17.9 Interrupt Inhibit Logic
    • 6.18 Power Fail/Auto Restart and Bootstrap Loader
      • 6.18.1 Power Fail/Auto Restart Block Diagram Description
      • 6.18.2 Power Fail/Auto Restart Programming
      • 6.18.3 Bootstrap Loader Block Diagram Description
    • 6.19 Bootstrap ROM Organization and Programming
      • 6.19.1 ROM Organization
      • 6.19.2 Auto-Restart/Bootstrap Sequence
      • 6.19.3 ROM Programming Examples
      • 6.19.4 Bootstrap Example
      • 6.19.5 Obtaining Blank ROMs
    • 6.20 ROM Program Listing
    • 6.21 Power Fail/Auto Restart and Bootstrap Operation and Timing
      • 6.21.1 Power Fail Operation
      • 6.21.2 Auto-Restart Operation and Timing
      • 6.21.3 Bootstrap Operation and Timing
    • 6.22 Power Fail/Auto-Restart and Bootstrap Operation Detailed Logic Description
      • 6.22.1 Power Fail/Auto-Restart Device Select and Operation Decoder
      • 6.22.2 Power Fail Interrupt and Skip Logic
      • 6.22.3 Bootstrap and Auto-Restart Timing Clock
      • 6.22.4 Bootstrap Initialization Logic
      • 6.22.5 Auto-Restart Initialization Logic
      • 6.22.6 Auto-Restart and Bootstrap Address Counters
      • 6.22.7 ROM Memory Control and Multiplexers
      • 6.22.8 Bootstrap and Auto-Restart Operation Control Logic
  • Chapter 7 Power Supply
    • 7.1 General
    • 7.2 PDP-8/A Semiconductor Basic Power Assembly
      • 7.2.1 Power Board
      • 7.2.2 Regulator Board (G8016)
        • 7.2.2.1 +5 Vdc Regulator Circuit
        • 7.2.2.2 +5 Vdc Regulator Circuit, Battery Operation
        • 7.2.2.3 Battery Empty Circuit
        • 7.2.2.4 Battery Charging Circuit
        • 7.2.2.5 ±15 Vdc Circuit
        • 7.2.2.6 POWER OK H Circuit
        • 7.2.2.7 AC LOW L Circuit
    • 7.3 8A400/600/800 Basic Power Assembly
      • 7.3.1 H9194 Connector Block Assembly
      • 7.3.2 Regulator Board (G8018)
        • 7.3.2.1 +5 Vdc Regulator Circuit
        • 7.3.2.2 -5 Vdc Regulator Circuit
        • 7.3.2.3 +20 Vdc Regulator Circuit
        • 7.3.2.4 ±15 Vdc Circuit
        • 7.3.2.5 POWER OK H Circuit
        • 7.3.2.6 AC LOW L Circuit
    • 7.4 8A420/620/820 Basic Power Assembly
      • 7.4.1 General
      • 7.4.2 Interlock and Triac Control Circuit
      • 7.4.3 Line Level Transformer and Peak Detector
      • 7.4.4 Thermistor/Thermostat and Emergency Shutdown
      • 7.4.5 POWER OK H Circuit
  • Chapter 8 Maintenance and Troubleshooting
    • 8.1 Maintenance and Troubleshooting Requirements
      • 8.1.1 Diagnostic Programs
      • 8.1.2 Equipment
    • 8.2 Preventive Maintenance Inspections
      • 8.2.1 Scheduled Maintenance
      • 8.2.2 The Importance of a Preventive Maintenance Schedule
    • 8.3 PDP-8/A Troubleshooting
      • 8.3.1 Operator Errors
      • 8.3.2 Troubleshooting Procedures
      • 8.3.3 Validation Tests
      • 8.3.4 Cable Problems
      • 8.3.5 Log Entry
      • 8.3.6 Removal and Replacement of Modules
      • 8.3.7 Removal and Replacement of Regulator Board
      • 8.3.8 Removal and Replacement of LEDs on the Limited Function Panel
      • 8.3.9 Removal and Replacement of LEDs on the Programmer's Console
    • 8.4 Power Supply Adjustments
      • 8.4.1 G8016 Power Supply Adjustment
        • 8.4.1.1 +5 V Adjustment (G8016)
      • 8.4.2 G8018 Power Supply Adjustment
        • 8.4.2.1 +5 V Power Supply Adjustment
        • 8.4.2.2 +20 V Power Supply Adjustment
    • 8.5 Power Fail/Auto-Restart Adjustment
      • 8.5.1 G8018 Power Fail/Auto-Restart Adjustment
      • 8.5.2 G8016 Power Fail/Auto-Restart Adjustment
    • 8.6 Line Voltage and Frequency Combinations
      • 8.6.1 8A400/600/800
      • 8.6.2 8A420/620/820
      • 8.6.3 PDP-8/A Semiconductor
  • Chapter 9 Spare Parts
  • Appendix A Instruction Summary
  • Appendix B Omnibus Signal Locator
  • Appendix C Module Assignment and Power Requirements
  • Appendix D Program Loading Procedures
    • D.1 Turning the System On
    • D.2 Read-In-Mode (RIM) Loader
    • D.3 Binary (BIN) Loader
    • D.4 Loading Binary Tapes
  • Appendix E ASCII Character Codes
  • Appendix F Device Codes
  • Appendix G Memory Cycle Time Summary
  • Appendix H Engineering Drawings

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