Appendix E. Challenge VMEbus Implementation
Prev |  | Next

## Appendix E. Challenge VMEbus Implementation

This appendix provides information to help users select third-party VME boards for the POWER Challenge and Challenge systems.

You may also wish to consult related books such as the following for additional background, as required.

- VMEbus Users's Handbook by Steve Heath

- Writing Device Drivers (P/N 007-0911-xxx)

| Warning: All board installations or removals should be performed only by Silicon Graphics trained or certified personnel. Unauthorized access to the cardcage area could result in system damage or even bodily harm, and could void warranty or safety agency approvals for the system.

## General Information

The VME interface in the Challenge system supports all protocols defined in Revision C of the VME specification, plus the A64 and D64 modes defined in Revision D. The D64 modes allows direct memory access (DMA) bandwidths of up to 60 MB.

| Note: The Challenge system does not support VSBbus mode.

For the acceptable VME address ranges, read the /var/sysgen/system file.

## VME Board Dimensions

The Challenge board slots have a 9U (vertical) form factor and measure 15.75 inches (400 mm) horizontally. The board edges must also be less than or equal to 0.062 inches (1.57 mm). If the board is thicker, the edge of the board must be milled to fit in the card guide. In addition, center-to-center board spacing is 0.8 inch (20.3 mm).

## Deskside VME Power and Cooling

The deskside Challenge provides five 9U VME slots. The system supplies approximately 40 watts of 5 V power per VME slot (nominally). The system provides 16.7 amps of 12 V power for the entire chassis. This provides approximately 0.25 to 0.5 amps (or 3 to 6 watts) per VME slot.

The deskside chassis circulates approximately 150 to 250 linear feet per minute (LFM) of air flow through the chassis (depending on the ambient temperature).

## Exceeding the Normal VME Power Rating Per Slot

If a VME board requires more than the normal slot power allotment, it is still possible the board can be used. However, two factors need to be carefully addressed—proper air flow and total power used.

To help maintain proper cooling, the board may also need special custom baffles, or perhaps a set of non-component, enclosure boards to surround the VME board with sufficient air flow. These custom air flow devices must be supplied by the customer.

A third-party VME board requiring greater than 40 watts of 5 V power can be used, as long as the board does not draw more than the amount of power allocated for VME board use. Generally speaking, this amount is approximately 150 watts of 5V power.

For example, you can install two 75-watt VME boards in a deskside system (providing the boards were sufficiently cooled). However, as a result, you could not install any additional VME boards, since the VME power allotment would already be saturated. In addition, it is also possible to use a single 150-watt VMEbus board, providing the remaining VME slots are also not used.

## Special VME Considerations

Generally, there are VME boards or devices that should not be integrated into the Challenge system. This section provides guidelines for selecting or designing third-party VME boards.

| Caution: Be sure to observe these general rules to avoid possible damage to the VMEbus and system.

- Devices acting as an A16 VME MASTER will not be able to access system memory via DMA.

- Devices should require 8-bit interrupt vectors only.

- Devices must not require UAT (unaligned transfers or tri-byte) access from the Challenge system.

- Devices in Slave mode must not require address modifiers, other than Supervisory/Nonprivileged data access.

- While in VME Master mode, devices must access only the system memory that uses Nonprivileged data access or Nonprivileged block transfers.

- Devices must have the ability to be configured so that their address range does not conflict with those used by the Challenge. Also, the device should be able to respond to an address generated by the system.

- The Challenge system does not support VSBbus boards.

- Be sure to place boards starting in slot 1, or jumper the daisy-chained signals across the empty slots. Otherwise, breaks occur in the interrupt acknowledge and bus arbitration schemes.

- Metal face plates or front panels on VME boards may need to be removed. The plate could prevent the I/O door from properly closing and possibly damage the I/O bulkhead.

Note that in some VME enclosures, these plates supply the required additional EMI shielding. However, the Challenge chassis already provides sufficient shielding for boards inside the chassis, so these plates are not necessary.

## VME Pins

Table E-1 through Table E-3 list the pin assignments of the VME P1, P2, and P3 connectors. Table E-4 describes the pin signals.

| Note: No connections are made to rows A and C of connector P2. These lines are not bused across the backplane. The P3 connector uses the SUN power convention. In addition, the Challenge system does not generate ACFAIL* or SYSFAIL*. The SERCLK and SERDAT* are also unused.

The Challenge system supplies the defined voltages to the bus and also asserts SYSREST* and drives SYSCLK (SYSCLK is driven at 16 MHz).

On Challenge system backplanes, the unused VME pins on P1/P2/P3 are no connects.

Table E-1. P1 VME Pin Assignments

Pin | Row A | Row B | Row C
--- | --- | --- | ---
1 | D00 | BBSY* | D08
2 | D01 | BCLR* | D09
3 | D02 | ACFAIL | D10
4 | D03 | BG01N* | D11
5 | D04 | BG0OUT* | D12
6 | D05 | BG1IN* | D13
7 | D06 | BG1OUT* | D14
8 | D07 | BG2IN* | D15
9 | GND | BG2OUT* | GND
10 | SYSCLK | BG3IN* | SYSFAIL*
11 | GND | BG3OUT* | BERR*
12 | DS1 | BR0* | SYSRESET*
13 | DS0 | BR1 | LWORD*
14 | WRITE* | BR2* | AM5
15 | GND | BR3* | A23
16 | DTACK* | AM0 | A22
17 | GND | AM1 | A21
18 | AS* | AM2 | A20
19 | GND | AM3 | A19
20 | IACK* | GND | A18
21 | IACKIN* | SERCLK | A17
22 | IACKOUT* | SERDAT* | A16
23 | AM4 | GND | A15
24 | A07 | IRQ7* | A14
25 | A06 | IRQ6* | A13
26 | A05 | IRQ5* | A12
27 | A04 | IRQ4* | A11
28 | A03 | IRQ3* | A10
29 | A02 | IRQ2* | A09
30 | A01 | IRQ1* | A08
31 | -12V | +5VSTDBY | +12V
32 | +5V | +5V | +5V

Table E-2. P2 VME Pin Assignments

Pin | Row A (Note: This row is user-defined.) | Row B | Row C (Note: This row is user-defined).
--- | --- | --- | ---
1 |  | +5V |
2 |  | GND |
3 |  | RESERVED |
4 |  | A24 |
5 |  | A25 |
6 |  | A26 |
7 |  | A27 |
8 |  | A28 |
9 |  | A29 |
10 |  | A30 |
11 |  | A31 |
12 |  | GND |
13 |  | +5V |
14 |  | D16 |
15 |  | D17 |
16 |  | D18 |
17 |  | D19 |
18 |  | D20 |
19 |  | D21 |
20 |  | D22 |
21 |  | D23 |
22 |  | GND |
23 |  | D24 |
24 |  | D25 |
25 |  | D26 |
26 |  | D27 |
27 |  | D28 |
28 |  | D29 |
29 |  | D30 |
30 |  | D31 |
31 |  | GND |
32 |  | +5V |

Table E-3. P3 VME Pin Assignments

Pin | Row A | Row B | Row C
--- | --- | --- | ---
1 through 25 | +5V | Not connected | GND
26, 27 | +12V | Not connected | +12V
28, 29 | -12V | Not connected | -12V
30 through 32 | -5V | Not connected | -5V

Table E-4. Signal Definitions

Signal Name | Definition
--- | ---
D00 through D31 | Data lines. These lines are tri-state and are not defined until the data strobes (DS0* and DS1*) are asserted by the MASTER.
A00 through A31 | Address lines. These lines are tri-state and are not defined until the address strobe (AS*) is asserted by the MASTER.
AM0 through AM5 | Address modifier lines. Asserted by the MASTER and indicates the type of data transfer to take place. VME SLAVEs look at the lines to determine if they will respond and what type of response to make.
DS0, DS1 | Data Strobe lines. Asserted by the MASTER and indicates stable data on the data bus.
AS | Address strobe. Is asserted by the MASTER and indicates a stable address is present on the address lines.
BR0 through BR3 | Bus request lines. The MASTER requests a busy bus via these prioritized levels.
BG0IN through BG3IN | Bus grant in (daisy-chained).
BG0OUT through BG3OUT | Bus grant out (daisy-chained).
BBSY | Busy.
BCLR | Bus clear. (Hint to bus master, VME MASTERs are not required to comply.)
IRQ1 - IRQ7 | Interrupt request lines.
IACK | Interrupt acknowledge. Asserted by MASTER to indicate the VME interrupt level to be serviced.
IACKIN | Interrupt acknowledge in (daisy-chained).
IACKOUT | Interrupt acknowledge in (daisy-chained).
DTACK | Data transfer acknowledge. Asserted by SLAVE to indicate a successful bus transfer.
WRITE | Write not or read.
LWORD | Indicates long word transfer (D32).
SYSCLK | 16 MHz system clock. (Does not control bus timing.)
SERCLK | Serial data clock.
SERDAT | Serial data line.
BERR | Bus error line.
SYSFAIL | Indicates a board has failed.
ACFAIL | AC power failure notify line.
SYSRESET | Reset signal for VME bus.

Prev | Table of Contents | Next
Appendix D. Challenge IO4 PROM, Mezzanine, and Troubleshooting |  | Index