This chapter describes the coprocessor instructions for these coprocessors:
System control coprocessor (cp0) instructions
Floating-point coprocessor instructions
See Chapter 5 for a description of the main processor's instructions and the coprocessor interface instructions.
The tables in this chapter list the assembler format for each coprocessor's load, store, computational, jump, branch, and special instructions. The format consists of an op-code and a list of operand formats. The tables list groups of closely related instructions; for those instructions, you can use any op-code with any specified operand.
 | Note: The system control coprocessor instructions do not have operands. |
Operands can have any of these formats:
Memory references: for example, a relocatable symbol +/– an expression(register)
Expressions (for immediate values)
Two or three operands: for example, ADD $3,$4 is the same as ADD $3,$3,$4
The following terms are used to discuss floating-point operations:
infinite: A value of +1 or –1.
infinity: A symbolic entity that represents values with magnitudes greater than the largest value in that format.
ordered: The usual result from a comparison, namely: <,=, or >.
NaN: Symbolic entities that represent values not otherwise available in floating-point formats. There are two kinds of NaNs. Quiet NaNs represent unknown or uninitialized values. Signaling NaNs represent symbolic values and values that are too big or too precise for the format. Signaling NaNs raise an invalid operation exception whenever an operation is attempted on them.
unordered: The condition that results from a floating-point comparison when one or both operands are NaNs.
The floating-point coprocessor has these classes of instructions:
Load and Store Instructions: Load values and move data between memory and coprocessor registers.
Move Instructions: Move data between registers.
Computational Instructions: Do arithmetic and logical operations on values in coprocessor registers.
Relational Instructions: Compare two floating-point values.
A particular floating-point instruction may be implemented in hardware, software, or a combination of hardware and software.
The formats for the single- and double-precision floating-point constants are shown below:
Floating-point load and store instructions must use even registers. The operands in Table 6-1 have the following meanings:
Operand | Meaning |
|---|---|
address | Offset (base) |
destination | Destination register |
source | Source register |
Description | Op-code | Operand |
|---|---|---|
Load Fp |
|
|
Load Indexed Fp |
|
|
Load Immediate Fp |
|
|
Store Fp |
|
|
Store Indexed Fp |
|
|
Double | L.D | destination, address |
Single | L.S |
|
Double | LDXC1 | destination, index(base) |
Single | LWXC1 |
|
Double | LI.D | destination, floating-point constant |
Single | LI.S |
|
Double | S.D | source, address |
Single | S.S |
|
Double | SDXC1 | destination, index(base) |
Single | SWXC1 |
|
This part of Chapter 6 groups the instructions by function. Please consult Table 6-1 for the op-codes. Table 6-1 describes the floating-point Load and Store instructions.
Table 6-1. Floating-Point Load and Store Descriptions
Instruction | Description |
|---|---|
Load Fp Instructions | Load eight bytes for double-precision and four bytes for single-precision from the specified effective address into the destination register, which must be an even register (32-bit only) . The bytes must be word aligned. Note: We recommend that you use doubleword alignment for double-precision operands. It is required in the MIPS2 architecture (R4000 and later). |
Load Indexed Fp Instructions | Indexed loads follow the same description as the load instructions above except that indexed loads use index+base to specify the effective address (64-bit only). |
Store Fp Instructions | Stores eight bytes for double-precision and four bytes for single-precision from the source floating-point register in the destination register, which must be an even register (32-bit only). Note: We recommend that you use doubleword alignment for double-precision operands. It is required in the MIPS2 architecture and later. |
Store Indexed Fp Instructions | Indexed stores follow the same description as the store instructions above except that indexed stores use index+base to specify the effective address (64-bit only). |
This part of Chapter 6 describes floating-point computational instructions. The operands in Table 6-3 and Table 6-4 have the following meaning:
Operand | Meaning |
|---|---|
destination | Destination register |
gpr | General-purpose register |
source | Source register |
Description | Op-code | Operand |
|---|---|---|
Absolute Value Fp |
|
|
Negate Fp |
|
|
Add Fp |
|
|
Divide Fp |
|
|
Multiply Fp |
|
|
Multiply Add FP |
|
|
Negative Multiply Add FP |
|
|
Multiply Subtract FP |
|
|
Negative Multiply Subtract FP |
|
|
Convert Source to Specified Fp Precision |
|
|
Truncate and Round Operations |
|
|
Double | ABS.D | destination, src1 |
Single | ABS.S |
|
Double | NEG.D |
|
Single | NEG.S |
|
Double | ADD.D | destination, src1, src2 |
Single | ADD.S |
|
Double | DIV.D |
|
Single | DIV.S |
|
Double | MUL.D |
|
Single | MUL.S |
|
Subtract Fp |
|
|
Double | SUB.D |
|
Single | SUB.S |
|
Double | MADD.D | destination, src1, src2, src3 |
Single | MADD.S |
|
Double | NMADD.D |
|
Single | NMADD.S |
|
|
|
|
Double | MSUB.D |
|
Single | MSUB.S |
|
Double | NMSUB.D |
|
Single | NMSUB.S |
|
Double to Single Fp | CVT.S.D | destination, src1 |
Fixed Point to Single Fp | CVT.S.W |
|
Single to Double Fp | CVT.D.S |
|
Fixed Point to Double Fp | CVT.D.W |
|
Single to Fixed Point Fp | CVT.W.S |
|
Double to Fixed Point Fp | CVT.W.D |
|
Truncate to Single Fp | TRUNC.W.S | destination, src, gpr |
Truncate to Double Fp | TRUNC.W.D |
|
Round to Single Fp | ROUND.W.S |
|
Round to Double Fp | ROUND.W.D |
|
Ceiling to Double Fp | CEIL.W.D |
|
Ceiling to Single Fp | CEIL.W.S |
|
Ceiling to Double Fp, Unsigned | CEILU.W.D |
|
Ceiling to Single Fp, Unsigned | CEILU.W.S |
|
Floor to Double Fp | FLOOR.W.D |
|
Floor to Single Fp | FLOOR.W.S |
|
Floor to Double F, Unsigned | FLOORU.W.D |
|
Floor to Single Fp Unsigned | FLOORU.W.S |
|
Round to Double Fp Unsigned | ROUNDU.W.D |
|
Round to Single Fp Unsigned | ROUNDU.W.S |
|
Truncate to Double Fp Unsigned | TRUNCU.W.D |
|
Truncate to Single Fp Unsigned | TRUNCU.W.S |
|
Description | Op-code | Operand |
|---|---|---|
Convert Source to Specified Fp Precision |
|
|
Truncate and Round Operations |
|
|
Reciprocal Approximation Operations |
|
|
Long Fixed Point to Single Fp | CVT.S.L | destination, src1 |
Long Fixed Point to Double FP | CVT.D.L |
|
Single to Long Fixed Point FP | CVT.L.S |
|
Double to Long Fixed Point FP | CVT.L.D |
|
Truncate Single to Long Fixed Point | TRUNC.L.S | destination, src, gpr |
Truncate Double to Long Fixed Point | TRUNC.L.D |
|
Round Single to Long Fixed Point | ROUND.L.S |
|
Round Double to Long Fixed Point | ROUND.L.D |
|
Ceiling Single to Long Fixed Point | CEIL.L.S |
|
Ceiling Double to Long Fixed Point | CEIL.L.D |
|
Floor Single to Long Fixed Point | FLOOR.L.S |
|
Floor Double to Long Fixed Point | FLOOR.L.D |
|
Reciprocal Approximation Single Fp | RECIP.S | destination, src1 |
Reciprocal Approximation Double Fp | RECIP.D |
|
Reciprocal Square Root Single Fp | RSQRT.S |
|
Reciprocal Square Root Double Fp | RSQRT.D |
|
This part of Chapter 6 groups the instructions by function. Refer to Table 6-3 and Table 6-4 for the op-code names. Table 6-2 describes the floating-point Computational instructions.
Table 6-2. Floating-Point Computational Instruction Descriptions
Instruction | Description |
|---|---|
Absolute Value Fp Instructions | Compute the absolute value of the contents of src1 and put the specified precision floating-point result in the destination register. |
Add Fp Instructions | Add the contents of src1 (or the destination) to the contents of src2 and put the result in the destination register. When the sum of two operands with opposite signs is exactly zero, the sum has a positive sign for all rounding modes except round toward –1. For that rounding mode, the sum has a negative sign. |
Convert Source to Another Precision Fp Instructions | Convert the contents of src1 to the specified precision, round according to the rounding mode, and put the result in the destination register. |
Mutiply-Then-Add Fp Instructions | Multiply the contents of src2 and src3, then add the result to src1 and store in the destination register (MADD). The NMADD instruction does the same mutiply then add, but then negates the sign of the result (64-bit only).. |
Mutiply-Then-Subtract Fp Instructions | Multiply the contents of src2 and src3, then subtract the result from src1 and store in the destination register (MSUB). The NMSUB instruction does the same mutiply then subtract, but then negates the sign of the result (64-bit only).. |
Truncate and Round instructions | The TRUNC instructions truncate the value in the source floating-point register and put the resulting integer in the destination floating-point register, using the third (general-purpose) register to hold a temporary value. (This is a macro-instruction.) The ROUND instructions work like TRUNC, but round the floating-point value to an integer instead of truncating it. |
Divide Fp Instructions | Compute the quotient of two values. These instructions treat src1 as the dividend and src2 as the divisor. Divide Fp instructions divide the contents of src1 by the contents of src2 and put the result in the destination register. If the divisor is a zero, the machine signals a error if the divide-by-zero exception is enabled. |
Multiply Fp Instructions | Multiplies the contents of src1 (or the destination) with the contents of src2 and puts the result in the destination register. |
Negate FP Instructions | Compute the negative value of the contents of src1 and put the specified precision floating-point result in the destination register. |
Subtract Fp Instructions | Subtract the contents of src2 from the contents of src1 (or the destination). These instructions put the result in the destination register. When the difference of two operands with the same signs is exactly zero, the difference has a positive sign for all rounding modes except round toward –1. For that rounding mode, the sum has a negative sign. |
Reciprocal Approximation Instructions | For RECIP, the reciprocal of the value in src1 is approximated and placed into the destination register. For RSQRT. the reciprocal of the square root of the value in src1 is approximated and placed into the destination register. |
Table 6-6 summarizes the floating-point relational instructions. The first column under Condition gives a mnemonic for the condition tested. As the “branch on true/false” condition can be used logically to negate any condition, the second column supplies a mnemonic for the logical negation of the condition in the first column. This provides a total of 32 possible conditions. The four columns under Relations give the result of the comparison based on each condition. The final column states if an invalid operation is signaled for each condition.
For example, with an equal condition (EQ mnemonic in the True column), the logical negation of the condition is not equal (NEQ), and a comparison that is equal is True for equal and False for greater than, less than, and unordered, and no Invalid Operation Exception is given if the relation is unordered.
Table 6-3. Floating-Point Relational Operators
Condition |
| Relations |
|
|
| Invalid Operation |
|---|---|---|---|---|---|---|
Mnemonic |
| Greater | Less | Equal | Unordered |
|
True | False |
|
|
|
|
|
F | T | F | F | F | F | no |
UN | OR | F | F | F | T | no |
EQ | NEQ | F | F | T | F | no |
UEQ | OLG | F | F | T | T | no |
OLT | UGE | F | T | F | F | no |
ULT | OGE | F | T | F | T | no |
OLE | UGT | F | T | T | F | no |
ULE | OGT | F | T | T | T | no |
SF | ST | F | F | F | F | yes |
NGLE | GLE | F | F | F | T | yes |
SEQ | SNE | F | F | T | F | yes |
NGL | GL | F | F | T | T | yes |
LT | NLT | F | T | F | F | yes |
NGE | GE | F | T | F | T | yes |
LE | NLE | F | T | T | F | yes |
NGT | GT | F | T | T | T | yes |
The mnemonics in the table above have following meanings:
Mnemonic | Meaning | Mnemonic | Meaning |
|---|---|---|---|
F | False | T | True |
UN | Unordered | OR | Ordered |
EQ | Equal | NEQ | Not Equal |
UEQ | Unordered or Equal | OLG | Ordered or Less than or Greater than |
OLT | Ordered Less Than | UGE | Unordered or Greater than or Equal |
ULT | Unordered or Less Than | OGE | Ordered Greater than or Equal |
OLE | Ordered Less than or Equal | UGT | Unordered or Greater Than |
ULE | Unorderd or Less than or Equal | OGT | Ordered Greater Than |
SF | Signaling False | ST | Signaling True |
NGLE | Not Greater than or Less than or Equal | GLE | Greater than, or Less than or Equal |
SEQ | Signaling Equal | SNE | Signaling Not Equal |
NGL | Not Greater than or Less than | GL | Greater Than or Less Less Than |
LT | Less Than | NLT | Not Less Than |
NGE | Not Greater Than | GE | Greater Than or Equal or Equal |
LE | Less Than or Equal | NLE | Not Less Than or Equal |
NGT | Not Greater Than | GT | Greater Than |
To branch on the result of a relational:
/* branching on a compare result */ c.eq.s $f1,$f2 /* compare the single-precision values */ bc1t true /* if $f1 equals $f2, branch to true */ bc1f false /* if $f1 does not equal $f2, branch to */ /* false */ |
These are the floating-point relational instruction formats.
Description | Op-code | Operand |
|---|---|---|
Compare OLE |
|
|
Compare ULE |
|
|
Compare SF |
|
|
Compare NGLE |
|
|
Compare SEQ |
|
|
Compare NGL |
|
|
*Compare LT |
|
|
Compare NGE |
|
|
*Compare LE |
|
|
Compare NGT |
|
|
Compare F |
|
|
Double | C.F.D | src1,src2 |
Single | C.F.S |
|
Compare UN |
|
|
Double | C.UN.D |
|
Single | C.UN.S |
|
*Compare EQ |
|
|
Double | C.EQ.D |
|
Single | C.EQ.S |
|
Compare UEQ |
|
|
Double | C.UEQ.D |
|
Single | C.UEQ.S |
|
Compare OLT |
|
|
Double | C.OLT.D |
|
Single | C>OLT.S |
|
Compare ULT |
|
|
Double | C.ULT.D |
|
Single | C.ULT.S |
|
Double | C.OLE.D |
|
Single | C.OLE.S |
|
Double | C.ULE.D |
|
Single | C.ULE.S |
|
Double | C.SF.D |
|
Single | C.SF.S |
|
Double | C.NGLE.D | src1, src2 |
Single | C.NGLE.S |
|
Double | C.SEQ.D |
|
Single | C.SEQ.S |
|
Double | C.NGL.D |
|
Single | C.NGL.S |
|
Double | C.LT.D |
|
Single | C.LT.S |
|
Double | C.NGE.D |
|
Single | C.NGE.S |
|
|
|
|
Double | C.LE.D |
|
Single | C.LE.S |
|
Double | C.NGT.D |
|
Single | C.NGT.S |
|
| Note: These are the most common Compare instructions. The MIPS coprocessor instruction set provides others for IEEE compatibility. |
This part of Chapter 6 describes the relational instruction descriptions by function. Refer to Chapter 1 for information regarding registers.
Table 6-4. Floating-Point Relational Instruction Descriptions
Instruction | Description |
|---|---|
Compare EQ Instructions | Compare the contents of src1 with the contents of src2. If src1 equals src2 a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
Compare F Instructions | Compare the contents of src1 with the contents of src2. These instructions always produce a false condition. The machine does not signal an exception for unordered values. |
Compare LE | Compare the contents of src1 with the contents of src2. If src1 is less than or equal to src2, a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare LT | Compare the contents of src1 with the contents of src2. If src1 is less than src2, a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare NGE | Compare the contents of src1 with the contents of src2. If src1 is less than src2 (or the contents are unordered), a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare NGL | Compare the contents of src1 with the contents of src2. If src1 equals src2 or the contents are unordered, a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare NGLE | Compare the contents of src1 with the contents of src2. If src1 is unordered, a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare NGT | Compare the contents of src1 with the contents of src2. If src1 is less than or equal to src2 or the contents are unordered, a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare OLE Instructions | Compare the contents of src1 with the contents of src2. If src1 is less than or equal to src2, a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
Compare OLT Instructions | Compare the contents of src1 with the contents of src2. If src1 is less than src2, a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
Compare SEQ Instructions | Compare the contents of src1 with the contents of src2. If src1 equals src2, a true condition results; otherwise, a false condition results. The machine signals an exception for unordered values. |
Compare SF Instructions | Compare the contents of src1 with the contents of src2. This always produces a false condition. The machine signals an exception for unordered values. |
Compare ULE Instructions | Compare the contents of src1 with the contents of src2. If src1 is less than or equal to src2 (or src1 is unordered), a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
Compare UEQ Instructions | Compare the contents of src1 with the contents of src2. If src1 equals src2 (or src1 and src2 are unordered), a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
Compare ULT Instructions | Compare the contents of src1 with the contents of src2. If src1 is less than src2 (or the contents are unordered), a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
Compare UN Instructions | Compare the contents of src1 with the contents of src2. If either src1 or src2 is unordered, a true condition results; otherwise, a false condition results. The machine does not signal an exception for unordered values. |
The floating-point move instructions move data from source to destination registers (only floating-point registers are allowed).
Description | Op-code | Operand |
|---|---|---|
Move FP |
|
|
Move Conditional on FP False |
|
|
Move Conditional on FP True |
|
|
Floating-Point Move Conditional on Not Zero |
|
|
Floating-Point Move Conditional on Zero |
|
|
Single | MOV.S | destination,src1 |
Double | MOV.D |
|
Single | MOVF.S | destination,src1, cc |
Double | MOVF.D |
|
Single | MOVT.S | destination,src1, cc |
Double | MOVT.D |
|
Single | MOVN.S | gpr_destination, gpr_src1, gpr |
Double | MOVF.D |
|
Single | MOVZ.S | gpr_destination, gpr_src1, gpr |
Double | MOVZ.D |
|
This part of Chapter 6 describes the floating-point move instructions.
Table 6-5. Floating-Point Move Instruction Descriptions
Instruction | Description |
|---|---|
Move FP Instructions | Move the double or single-precision contents of src1 to the destination register, maintaining the specified precision,if the condition code (cc) is zero (MOVF) or is one (MOVT). |
Conditonal FP Move Instructions | Conditionally, move the double-precision or single-precision contents of src1 to the destination register, maintaining the specified precision. |
Floating-Point Conditonal Move Instructions | Conditionally, move a floating-point value from src1 to the destination register if the gpr_register is zero (MOVZ) or not equal to zero (MOVN). |
The system control coprocessor (cp0) handles all functions and special and privileged registers for the virtual memory and exception handling subsystems. The system control coprocessor translates addresses from a large virtual address space into the machine's physical memory space. The coprocessor uses a translation lookaside buffer (TLB) to translate virtual addresses to physical addresses.
These coprocessor system control instructions do not have operands.
Description | Op-code |
|---|---|
Cache** | CACHE |
Translation Lookaside Buffer Probe | TLBP |
Translation Lookaside Buffer Read | TLBR |
Translation Lookaside Buffer Write Random | TLBWR |
Translation Lookaside Write Index | TLBWI |
Synchronize* | SYNC |
| |
|
This part of Chapter 6 describes the system control coprocessor instructions.
Table 6-6. System Control Coprocessor Instruction Descriptions
Instruction | Description |
|---|---|
Cache (CACHE) ** | Cache is the R4000 instruction to perform cache
operations. The 16-bit offset is sign-extended and
added to the contents of general register base to form
a virtual address. The virtual address is translated to
a physical address using the TLB. The 5-bit
sub-opcode (“op”) specifies the cache operation for
that address. Part of the virtual address is used to
specify the cache block for the operation. Possible
operations include invalidating a cache block,
writeback to a secondary cache or memory, etc. |
Translation Lookaside Buffer Probe (TLBP) | Probes the translation lookaside buffer (TLB) to see if the TLB has an entry that matches the contents of the EntryHi register. If a match occurs, the machine loads the Index register with the number of the entry that matches the EntryHi register. If no TLB entry matches, the machine sets the high-order bit of the Index register. |
Translation Lookaside Buffer Read (TLBR) | Loads the EntryHi and EntryLo registers with the contents of the translation lookaside buffer (TLB) entry specified in the TLB Index register. |
Translation Lookaside BufferWrite Random (TLBWR) | Loads the specified translation lookaside buffer (TLB) entry with the contents of the EntryHi and EntryLo registers. The contents of the TLB Random register specify the TLB entry to be loaded. |
Translation Lookaside Buffer Write Index (TLBWI) | Loads the specified translation lookaside buffer (TLB) entry with the contents of the EntryHI and EntryLO registers. The contents of the TLB Index register specify the TLB entry to be loaded. |
Synchronize (SYNC) * | Ensures that all loads and stores fetched before the
sync are completed, before allowing any following
loads or stores. Use of sync to serialize certain
memory references may be required in
multiprocessor environments. |
Floating-point coprocessor control register 31 contains status and control information. It controls the arithmetic rounding mode and the enabling of user-level traps, and indicates exceptions that occurred in the most recently executed instruction, and any exceptions that may have occurred without being trapped:
The exception bits are set for instructions that cause an IEEE standard exception or an optional exception used to emulate some of the more hardware-intensive features of the IEEE standard.
The exception field is loaded as a side-effect of each floating-point operation (excluding loads, stores, and unformatted moves). The exceptions which were caused by the immediately previous floating-point operation can be determined by reading the exception field.
The meaning of each bit in the exception field is given below. If two exceptions occur together on one instruction, the field will contain the inclusive-OR of the bits for each exception:
Exception Field Bit | Description |
|---|---|
E | Unimplemented Operation |
I | Inexact Exception |
O | Overflow Exception |
U | Underflow Exception |
V | Invalid Operation |
Z | Division-by-Zero |
The unimplemented operation exception is normally invisible to user-level code. It is provided to maintain IEEE compatibility for non-standard implementations.
The five IEEE standard exceptions are listed below:
Field | Description |
|---|---|
I | Inexact Exception |
O | Overflow Exception |
U | Underflow Exception |
V | Invalid Operationz |
Z | Division-by-Zero |
Each of the five exceptions is associated with a trap under user control, which is enabled by setting one of the five bits of the enable field, shown above.
When an exception occurs, both the corresponding exception and status bits are set. If the corresponding enable flag bit is set, a trap is taken. In some cases the result of an operation is different if a trap is enabled.
The status flags are never cleared as a side effect of floating-point operations, but may be set or cleared by writing a new value into the status register, using a “move to coprocessor control” instruction.
The floating-point compare instruction places the condition which was detected into the `c' bit of the control and status register, so that the state of the condition line may be saved and restored. The `c' bit is set if the condition is true, and cleared if the condition is false, and is affected only by compare and move to control register instructions.
For each IEEE standard exception, a status flag is provided that is set on any occurrence of the corresponding exception condition with no corresponding exception trap signaled. It may be reset by writing a new value into the status register. The flags may be saved and restored individually, or as a group, by software. When no exception trap is signaled, a default action is taken by the floating-point coprocessor, which provides a substitute value for the original, exceptional, result of the floating-point operation. The default action taken depends on the type of exception, and in the case of the Overflow exception, the current rounding mode.
The invalid operation exception is signaled if one or both of the operands are invalid for an implemented operation. The result, when the exception occurs without a trap, is a quiet NaN when the destination has a floating-point format, and is indeterminate if the result has a fixed-point format. The invalid operations are:
Addition or subtraction: magnitude subtraction of infinities, such as
( + 1 ) – ( – 1 ).Multiplication: 0 times 1, with any signs.
Division: 0 over 0 or 1 over 1, with any signs.
Square root of x: where x is less than zero.
Conversion of a floating-point number to a fixed-point format when an overflow, or operand value of infinity or NaN, precludes a faithful representation in that format.
Comparison of predicates involving < or > without ?, when the operands are “unordered”.
Any operation on a signaling NaN.
Software may simulate this exception for other operations that are invalid for the given source operands. Examples of these operations include IEEE-specified functions implemented in software, such as Remainder: x REM y, where y is zero or x is infinite; conversion of a floating-point number to a decimal format whose value causes and overflow or is infinity of NaN; and transcendental functions, such as ln (–5) or cos-1(3).
The division by zero exception is signaled on an implemented divide operation if the divisor is zero and the dividend is a finite nonzero number. The result, when no trap occurs, is a correctly signed infinity.
If division by zero traps are enabled, the result register is not modified, and the source registers are preserved.
Software may simulate this exception for other operations that produce a signed infinity, such as ln(0), sec(p/2), csc(0) or 0-1.
The overflow exception is signaled when what would have been the magnitude of the rounded floating-point result, were the exponent range unbounded, is larger than the destination format's largest finite number. The result, when no trap occurs, is determined by the rounding mode and the sign of the intermediate result.
If overflow traps are enabled, the result register is not modified, and the source registers are preserved.
Two related events contribute to underflow. One is the creation of a tiny non-zero result between \xb1 2Emin (minimum expressible exponent) which, because it is tiny, may cause some other exception later. The other is extraordinary loss of accuracy during the approximation of such tiny numbers by denormalized numbers.
The IEEE standard permits a choice in how these events are detected, but requires that they must be detected the same way for all operations.
The IEEE standard specifies that “tininess” may be detected either: “after rounding” (when a nonzero result computed as though the exponent range were unbounded would lie strictly between \xb1 2Emin), or “before rounding” (when a nonzero result computed as though the exponent range and the precision were unbounded would lie strictly between \xb1 2Emin). The architecture requires that tininess be detected after rounding.
Loss of accuracy may be detected as either “denormalization loss” (when the delivered result differs from what would have been computed if the exponent range were unbounded), or “inexact result” (when the delivered result differs from what would have been computed if the exponent range and precision were both unbounded). The architecture requires that loss of accuracy be detected as inexact result.
When an underflow trap is not enabled, underflow is signaled (via the underflow flag) only when both tininess and loss of accuracy have been detected. The delivered result might be zero, denormalized, or \xb1 2Emin. When an underflow trap is enabled, underflow is signaled when tininess is detected regardless of loss of accuracy.
If underflow traps are enabled, the result register is not modified, and the source registers are preserved.
If the rounded result of an operation is not exact or if it overflows without an overflow trap, then the inexact exception is signaled. The rounded or overflowed result is delivered to the destination register, when no inexact trap occurs. If inexact exception traps are enabled, the result register is not modified, and the source registers are preserved.
If an operation is specified that the hardware may not perform, due to an implementation restriction on the supported operations or supported formats, an unimplemented operation exception may be signaled, which always causes a trap, for which there are no corresponding enable or flag bits. The trap cannot be disabled.
This exception is raised at the execution of the unimplemented instruction. The instruction may be emulated in software, possibly using implemented floating-point unit instructions to accomplish the emulation. Normal instruction execution may then be restarted.
This exception is also raised when an attempt is made to execute an instruction with an operation code or format code which has been reserved for future architectural definition. The unimplemented instruction trap is not optional, since the current definition contains codes of this kind.
This exception may be signaled when unusual operands or result conditions are detected, for which the implemented hardware cannot handle the condition properly. These may include (but are not limited to), denormalized operands or results, NaN operands, trapped overflow or underflow conditions. The use of this exception for such conditions is optional.
Bits 0 and 1 of the coprocessor control register 31 sets the rounding mode for floating-point. The machine allows four rounding modes:
Round to nearest rounds the result to the nearest representable value. When the two nearest representable values are equally near, this mode rounds to the value with the least significant bit zero. To select this mode, set bits 1..0 of control register 31 to 0.
Round toward zero rounds toward zero. It rounds to the value that is closest to and not greater in magnitude than the infinitely precise result. To select this mode, set bits 1..0 of control register 31 to 1.
Round toward positive infinity rounds to the value that is closest to and not less than the infinitely precise result. To select this mode, set bits 1..0 of control register 31 to 2.
Round toward negative infinity rounds toward negative infinity. It rounds to the value that is closest to and not greater than the infinitely precise result. To select this mode, set bits 1..0 of control register 31 to 3.
To set the rounding mode:
/* setting the rounding mode */
RoundNearest = Ox0
RoundZero = Ox1
RoundPosInf = Ox2
RoundNegInf = Ox3
cfc1 rt2, $31 # move from coprocessor 1
and rt, Oxfffffffc # zero the round mode bits
or rt, RoundZero # set mask as round to zero
ctc1 rt, $f31 # move to coprocessor 1
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