6.14 Interrupts
Timer Interrupt
The timer interrupt is accessible as bit 15 of the Cause register, IP[7], as shown in Figure 6-5. This bit is set when one of the following occurs:
- the Count register is equal to the Compare register
- either one of the two performance counters overflows
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
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