9. Error Protection and Handling

9.3 Propagation of Uncorrectable Errors

• During external block data response cycles, if the data quality indication on SysCmd(5) is asserted, or if an uncorrectable ECC error is encountered on the system address/data bus while the ECC check indication on SysCmd(0) is asserted, the processor intentionally corrupts the ECC of the corresponding secondary cache quadword after receiving an external ACK completion response.
• During processor data cycles, the processor asserts the data quality indication on SysCmd(5) if the data is known to contain uncorrectable errors. The System interface ECC is never intentionally corrupted; the SysCmd(5) bit is used to indicate corrupted data.
• If an uncorrectable cache tag error is detected, the processor asserts SysUncErr* for one SysClk cycle.
• An external coherency request that detects a secondary cache tag array uncorrectable error asserts the secondary cache block tag quality indication on SysState(2) during the corresponding processor coherency state response.
• If an external coherency request requires a processor coherency data response, and a primary data cache tag parity error is encountered during the primary cache interrogation, or a secondary cache tag array uncorrectable error is encountered during the secondary cache interrogation, the processor asserts the data quality indication on SysCmd(5) for all doublewords of the corresponding processor coherency data response.