12.1 DC Electrical Specification

DC Input/Output Specifications

All processor output drivers are CMOS push-pull, and the signals swing between VccQ and Vss. In open drain mode, the gates of the PMOS pullup devices are disabled. Input-only pins include a disabled output buffer for implicit ESD protection.

Tables 12-2 and 12-3 describe the DC characteristics of the I/O signals for the HSTL and CMOS/TLL configurations.

NOTE: As the JEDEC Standard 8-x evolves, the HSTL specifications will also change, and the processor will remain compliant with these standards.

Table 12-2 DC Characteristics for HSTL Configuration

Table 12-3 DC Characteristics for CMOS/TTL Configuration

All the JTAG output drivers are push-pull CMOS/TTL compatible, with Vcc (core) as the supply (independent of VccQ[SC, Sys]). All the JTAG inputs require full CMOS swings, as given by the DC specifications in the Table 12-3.

Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96

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