14. Coprocessor 0

14.10 Status Register (12)

The Status register (SR) is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. The following list describes the more important Status register fields; Figure 14-11 shows the format of the entire register, and Table 14-10 describes the Status register fields.

Some of the important fields include:

The 4-bit Coprocessor Usability (CU) field controls the usability of 4 possible coprocessors. Regardless of the CU0 bit setting, CP0 is always usable in Kernel mode. The XX bit enables the MIPS IV ISA in User mode.
By default, the R10000 processor implements the same user instruction set as the R4400 processor. To enable execution of the MIPS IV instructions in User mode, the MIPS IV User Mode bit, (XX) of the CP0 Status register must be set.

The MIPS IV instruction extension uses COP1X as the opcode; this designation was COP3 in the R4400 processor. For this reason the CU3 bit is omitted in the R10000 processor, and is used as the XX bit. In Kernel and Supervisor modes, the state of the XX bit is ignored, and MIPS IV instructions are always available.

Mode bit settings are shown in Table 14-9; dashes in the table represent don't cares.

Table 14-9 ISA and Status Register Settings for User, Supervisor and
Kernel Mode Operations

NOTE: Operation with the MIPS IV ISA does not assume or require that the MIPS III instruction set or 64-bit addressing be enabled -- KX, SX and UX may all be set to zero.

The Reduced Power (RP) bit is reserved and should be zero. The R10000 processor does not define a reduced power mode.
The Reverse-Endian (RE) bit, bit 25, reverses the endianness of the machine. The processor can be configured as either little-endian or big-endian at system reset; reverse-endian selection is available in Kernel and Supervisor modes, and in the User mode when the RE bit is 0. Setting the RE bit to 1 inverts the User mode endianness.
The 9-bit Diagnostic Status (DS) field is used for self-testing, and checks the cache and virtual memory system. This field is described in Table 14-11 and Figure 14-12.
The 8-bit Interrupt Mask (IM) field controls the enabling of eight interrupt conditions. Interrupts must be enabled before they can be asserted, and the corresponding bits are set in both the Interrupt Mask field of the Status register and the Interrupt Pending field of the Cause register.
The processor mode is undefined if the KSU field is set to 3 (112). The R10000 processor implements this as User mode.

Figure 14-11 Status Register

Generated with CERN WebMaker