14. Coprocessor 0
Each counter is a 32-bit read/write register and is incremented by one each time the countable event, specified in its associated control register, occurs. Each counter can independently count one type of event at a time.
The counter asserts an interrupt, IP[7], when its most significant bit (bit 31) becomes one (the counter overflows) and the associated performance control register enables the interrupt.
The counting continues after counter overflow whether or not an interrupt is signalled.
The format of the control registers are shown in Figure 14-22.
Figure 14-22 Control Register Format
The fields of the Control register are:
Made various changes to Table 14-18, as indicated by the underlines. Note that the updated material reflects the functionality of silicon revision 3.0 and later. The status of earlier silicon revisions are documented as silicon errata available on
http://www.mips.com.
In describing the rules that are applied for the counting of each events listed in Table 14-18, following terminology is used:
Done is defined as the point at which the instruction is successfully executed by the functional unit but is not yet graduated.
Graduated is defined as the point in time when the instruction is successfully executed (done), and it is the oldest instruction.
Secondary Cache Transaction Processing (SCTP) logic is on-chip logic in which up to four internally-generated and one-externally generated secondary cache transactions are queued to be processed.
The following rules apply for the counting of each event listed in Table 14-16:
Event 0 for Counter 0 and Counter 1: Cycles
The counter is incremented on each PClk cycle.
Event 1 for Counter 0: Instructions Issued
The counter is incremented on each cycle by the sum of the three following events:
The counter is incremented by the number of instructions that were graduated on the previous cycle. When an integer multiply or divide instruction graduates, it is counted as two instructions.
Event 2 for Counter 0: Load/Prefetch/Sync/CacheOp Issue.
Each of these instructions are counted as they are issued. A load instruction is only counted once, even though it may have been issued more than one
time.
Event 2 for Counter 1: Load/Prefetch/Sync/CacheOp Graduation.
Each of these instructions are counted as they are graduated. Up to four loads can graduate in one cycle.
Event 3 for Counter 0: Stores (Including Store-Conditional) Issued.
The counter is incremented on the cycle after a store instruction is issued to the address-calculation unit. Note that a store can only be counted as having been issued once, even though it may actually be issued more than once due to DCache Tag being busy or there already being four load/store cache misses waiting in the SCTP logic.
Event 3 For Counter 1: Store (Including Store-Conditional) Graduation.
Each graduating store (including SC) increments the counter. At most one store can graduate per cycle.
Event 4 for Counter 0: Store-Conditional Issued.
This counter is incremented on the cycle after a store conditional instruction is issued to the address-calculation unit. Note that an SC can only be counted as having been issued once, even though it may actually be issued more than once due to DCache Tag being busy or there already being four load/store cache misses waiting in the SCTP logic.
Event 4 for Counter 1: Store-Conditional Graduation.
At most, one store-conditional can graduate per cycle. This counter is incremented on the cycle following the graduation of a store-conditional instruction.
Event 5 for Counter 0: Failed Store Conditional.
This counter is incremented when a store-conditional instruction fails.
Event 5 for Counter 1: Floating-Point Instruction Graduation.
This counter is incremented by the number of FP instructions which graduated on the previous cycle. Any instruction that sets the FP Status register bits (EVZOUI) is counted as a graduated floating point instruction. There can be 0 to 4 such instructions each cycle.
Event 6 for Counter 0: Conditional Branch Resolved
This counter is incremented when a conditional branch is determined to have been "resolved."*2 Note that when multiple floating-point conditional branches are resolved in a single cycle, this counter is still only incremented by one. Although this is a rare event, in this case the count would be incorrect.
Event 6 for Counter 1: Quadwords Written Back From Primary Data Cache
This counter is incremented once each cycle that a quadword of data is written from primary data cache to secondary cache.
Event 7 for Counter 0: Quadwords Written Back From Secondary Cache
This counter is incremented once each cycle that a quadword of data is written back from the secondary cache to the outgoing buffer located in the on-chip system-interface unit. (Note that data from the outgoing buffer could be invalidated by an external request and not sent out of the processor.)
Event 7 for Counter 1: TLB Refill Exception (Due To TLB Miss)
This counter is incremented on the cycle after the TLB miss handler is invoked. All TLB misses are counted, whether they occur in the native code or within the TLB handler.
Event 8 for Counter 0: Correctable ECC Errors On Secondary Cache Data.
This counter is incremented on the cycle after the correction of a single-bit error on a quadword read from the secondary cache data array.
Event 8 for Counter 1: Branch Misprediction.
This counter is incremented on the cycle after a branch is restored because of misprediction. Note that the misprediction is determined on the same cycle that the conditional branch is resolved. The misprediction rate is the ratio of branch mispredicted count to conditional branch resolve count.
Event 9 for Counter 0: Primary Instruction Cache Misses.
This counter is incremented one cycle after an instruction refill request is sent to the SCTP logic.
Event 9 for Counter 1: Secondary Cache Load/Store and Cache-ops Operations
This counter is incremented one cycle after a request is entered into the SCTP logic, provided the request was initially targeted at the primary data cache. Such requests fall into three categories:
This counter is incremented the cycle after the last quadword of a primary instruction cache line is written from the main memory, while the secondary cache refill continues.
Event 10 for Counter 1: Secondary Cache Misses (Data)
This counter is incremented the cycle after the second quadword of a data cache line is written from the main memory, while the secondary cache refill continues.
Event 11 for Counter 0: Secondary Cache Way Misprediction (Instruction)
This counter is incremented when the secondary cache controller begins to retry an access to the secondary cache after it hit in the non-predicted way, provided the secondary cache access was initiated by the primary instruction cache.
Event 11 for Counter 1: Secondary Cache Way Misprediction (Data)
This counter is incremented when the secondary cache controller begins to retry an access to the secondary cache because it hit in the non-predicted way, provided the secondary cache access was initiated by the primary data cache.
Event 12 for Counter 0: External Intervention Requests
This counter is incremented on the cycle after an external intervention request enters the SCTP logic.
Event 12 for Counter 1: External Intervention Requests Hits In Secondary Cache
This counter is incremented on the cycle after an external intervention request is determined to have hit in the secondary cache.
Event 13 for Counter 0: External Invalidate Requests
This counter is incremented on the cycle after an external invalidate request enters the SCTP logic.
Event 13 for Counter 1: External Invalidate Requests Hits In Secondary Cache
This counter is incremented on the cycle after an external invalidate request is determined to have hit in the secondary cache.
Event 14 for Counter 0: Functional Unit Completion Cycles
This counter is incremented once on the cycle after at least one of the functional units -- ALU1, ALU2, FPU1, or FPU2 -- marks an instruction as done.
Event 14 for Counter 1: Stores, or Prefetches with Store Hint to Clean Exclusive Secondary Cache Blocks.
This counter is incremented on the cycle after a request to change the Clean Exclusive state of the targeted secondary cache line to Dirty Exclusive is sent to the SCTP logic.
Event 15 for Counter 0: Instruction Graduation.
This counter is incremented by the number of instructions that were graduated on the previous cycle. When an integer multiply or divide instruction graduates, it is counted as two graduated instructions.
Event 15 for Counter 1: Stores or Prefetches with Store Hint to Shared Secondary Cache Blocks.
This counter is incremented on the cycle after a request to change the Shared state of the targeted secondary cache line to Dirty Exclusive is sent to the SCTP logic.
Table 14-19 Writing Performance Registers Using MTC0 
The performance counters and associated control registers are read by using a MFC0 instruction, as shown in Table 14-20.
Table 14-20 Reading Performance Registers Using MFC0 
The format of the performance control registers are shown in Table 14-21.
Table 14-21 Performance Control Register Format 
The count enable field specifies whether counting is to be enabled during User, Supervisor, Kernel, and/or Exception level mode. Any combination of count enable bits may be asserted.
All unused bits in the performance control registers are reserved.
All counting is disabled when the ERL bit of the CP0 Status register is asserted.
Table 14-22 defines the operation of the count enable bits of the performance control registers.
Table 14-22 Count Enable Bit Definition 
The following rules apply:
