14. Coprocessor 0
The R10000 processor defines two performance counters, and their associated event specifier registers, which are mapped into the CP0 register 25. The following instructions are used to perform an MTC0 to or an MFC0 from a performance counter or an event specifier register. The event specifier registers are referred as control registers in the description of CP0 register 25.
Format: MFPC rt, reg -- Move from performance counter
reg can be either a performance counter or an event specifier; only register 0 and 1 are valid in the R10000 implementation.
The 0 field in each instruction is changed from a 1 to a 0.
MTPC rt, reg -- Move to performance counter
MFPS rt, reg -- Move from performance event specifier
MTPS rt, reg -- Move to performance event specifier
