R10000 Microprocessor User's Manual

15. Floating-Point Unit

This section describes the operation of the FPU, including the register definitions.

The Floating-Point unit consists of the following functional units:

The add unit performs floating-point add and subtract, compare, and conversion operations. Except for Convert Integer To Single-Precision (float), all operations have a 2-cycle latency and a 1-cycle repeat rate.

The multiply unit performs single-precision or double-precision multiplication with a 2-cycle latency and a 1-cycle repeat rate.

The divide and square-root units do single- or double-precision operations. They have long latencies and low repeat rates (20 to 40 cycles).

Chapter Contents

15.1 - Floating Point Unit Operations
15.2 - Floating-Point Unit Control
15.3 - Floating-Point General Registers (FGRs)
15.4 - Floating-Point Control Registers
15.5 - FPU Instructions

Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96

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