R10000 Microprocessor User's Manual
18. Cache Test Mode
The R10000 processor provides a cache test mode that may be used during manufacturing test and system debug to access the following internal RAM arrays:
- data cache data array
- data cache tag array
- instruction cache data array
- instruction cache tag array
- secondary cache way predication table
Chapter Contents
- 18.1 - Interface Signals
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- 18.2 - System Interface Clock Divisor
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- 18.3 - Entering Cache Test Mode
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- 18.4 - Exit Sequence
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- 18.5 - SysAD(63:0) Encoding
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- 18.6 - Cache Test Mode Protocol
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- A.1 - Superscalar Processor
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- A.2 - Pipeline
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- A.3 - Pipeline Latency
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- A.4 - Pipeline Repeat Rate
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- A.5 - Out-of-Order Execution
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- A.6 - Dynamic Scheduling
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- A.7 - Instruction Fetch, Decode, Issue, Execution, Completion, and Graduation
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- A.8 - Active List
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- A.9 - Free List and Busy Registers
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- A.10 - Register Renaming
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- A.11 - Nonblocking Loads and Stores
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- A.12 - Speculative Branching
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- A.13 - Logical and Physical Registers
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- A.14 - Register Files
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- A.15 - ANDES Architecture
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Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
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