18. Cache Test Mode
18.2 System Interface Clock Divisor
Cache test mode is supported for all system interface clock speeds. However, since cache test mode repeat rates and latencies are expressed in terms of PClk cycles, the external agent must take care when operating at any system interface clock divisor other than Divide-by-1.
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
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