18.6 Cache Test Mode Protocol
Auto-Increment Read Protocol
A cache test mode auto-increment read operation reads a selected RAM array. The read address is obtained by incrementing the previous access address, and the read way is obtained from the previous access way.
If an overflow occurs when incrementing the previous access address, the address wraps to 0, and the way is toggled.
The external agent issues an auto-increment read command by:
- asserting the auto-increment select on SysAD(44)
- negating the Write/Read select on SysAD(43)
- driving the array select on SysAD(42:40)
- asserting SysVal* for one SysClk cycle.
After a read latency of 15 PClk cycles, the processor provides the read response by:
- entering Master state
- driving the read data on SysAD(39:0)
- asserting SysVal* for one SysClk cycle.
In the following SysClk cycle, the processor reverts to Slave state.
Auto-increment reads have a repeat rate of 17 PClk cycles.
Figure 18-6 depicts two cache test mode auto-increment reads.
Figure 18-6 Cache Test Mode Auto-Increment Read Protocol
A. Glossary
The following terms are defined in this Glossary:
- superscalar processor
- pipeline
- pipeline latency
- pipeline repeat rate
- out-of-order execution
- dynamic scheduling
- instruction fetch, decode, issue, execution, completion, and graduation
- active list
- free list and busy registers
- register renaming and unnaming
- nonblocking loads and stores
- speculative branching
- logical and physical registers
- register files
- ANDES architecture
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
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