SYNC instruction is implemented in a "lightweight" manner: after decoding a SYNC instruction, the processor continues to fetch and decode further instructions. It is allowed to issue load and store instructions speculatively and out-of-order, following a SYNC.
The R10000 processor only allows a SYNC instruction to graduate when the following conditions are met:
- all previous instructions have been successfully completed
- the uncached buffer does not contain any uncached stores
- the address cycle of a processor double/single/partial-word write request resulting from an uncached store was not issued to the System interface in any of the prior three SysClk cycles
- the SysGblPerf* signal is asserted
A SYNC instruction is not prevented from graduating if the uncached buffer contains any uncached accelerated stores.
