5. Secondary Cache Interface

5.6 Read Sequences

sequences:

• a 4-word read
• an 8-word read
• a 16-word read
• a 32-word read
• a tag read

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The SCClk referred in the secondary cache read and write timing diagrams is an internal SCClk. The relationship between this internal SCClk and the external SCClk[5:0]/SCClk[5:0]* can be programmed during boot time by setting the SCClkTap mode bits (see the section titled "Mode Bits" in Chapter 8 for detail on mode bits).