<?xml version="1.0" encoding="ISO-8859-1"?>
<toc>
<book href="index.html" id="id5381062">
<title>REACT&#8482; Real-Time 
Programmer's Guide</title>
<bookinfo href="front.html">
<title>Front Matter</title>
</bookinfo>
<preface href="pr01.html" id="id5384646">
<title>New Features in This Guide</title>
<section href="pr01.html#id5439374" id="id5439374">
<title>New Features Documented</title>
</section>
</preface>
<preface href="pr02.html" id="id5178904">
<title>About This Guide</title>
<section href="pr02.html#id5178964" id="id5178964">
<title>Who This Guide Is For</title>
</section>
<section href="pr02.html#id5179010" id="id5179010">
<title>What This Guide Contains</title>
</section>
<section href="pr02.html#LE96700-PARENT" id="LE96700-PARENT">
<title>Related Publications and Sites</title>
</section>
<section href="pr02.html#id5179300" id="id5179300">
<title>Obtaining Publications</title>
</section>
<section href="pr02.html#id5179412" id="id5179412">
<title>Conventions</title>
</section>
<section href="pr02.html#id5179617" id="id5179617">
<title>Reader Comments</title>
</section>
</preface>
<chapter href="ch01.html" id="LE12360-PARENT">
<title>Chapter 1. Real-Time Programs</title>
<section href="ch01.html#id5179762" id="id5179762">
<title>Defining Real-Time Programs</title>
</section>
<section href="ch01.html#id5179804" id="id5179804">
<title>Examples of Real-Time Applications</title>
<section href="ch01.html#id5179954" id="id5179954">
<title>Simulators</title>
<section href="ch01.html#id5177353" id="id5177353">
<title>Frame Rate</title>
</section>
<section href="ch01.html#id5177414" id="id5177414">
<title>Transport Delay</title>
</section>
<section href="ch01.html#id5177482" id="id5177482">
<title>Aircraft Simulators</title>
</section>
<section href="ch01.html#id5177528" id="id5177528">
<title>Ground Vehicle Simulators</title>
</section>
<section href="ch01.html#id5177586" id="id5177586">
<title>Plant Control Simulators</title>
</section>
<section href="ch01.html#id5177675" id="id5177675">
<title>Virtual Reality Simulators</title>
</section>
<section href="ch01.html#id5177770" id="id5177770">
<title>Hardware-in-the-Loop Simulators</title>
</section>
</section>
<section href="ch01.html#id5177815" id="id5177815">
<title>Data Collection Systems</title>
</section>
</section>
<section href="ch01.html#id5178036" id="id5178036">
<title>Real-Time Programming Languages</title>
</section>
</chapter>
<chapter href="ch02.html" id="LE34779-PARENT">
<title>Chapter 2. How IRIX and REACT/pro Support Real&#8211;Time Programs</title>
<section href="ch02.html#LE93209-PARENT" id="LE93209-PARENT">
<title>Kernel Facilities for Real-Time Programs</title>
<section href="ch02.html#id5178231" id="id5178231">
<title>Kernel Optimizations</title>
</section>
<section href="ch02.html#id5178288" id="id5178288">
<title>Special Scheduling Disciplines</title>
<section href="ch02.html#id5178304" id="id5178304">
<title>POSIX Real-Time Policies</title>
</section>
<section href="ch02.html#id5178331" id="id5178331">
<title>Gang Scheduling</title>
</section>
</section>
<section href="ch02.html#id5178441" id="id5178441">
<title>Locking Virtual Memory</title>
</section>
<section href="ch02.html#id5178513" id="id5178513">
<title>Mapping Processes and CPUs</title>
</section>
<section href="ch02.html#id5187678" id="id5187678">
<title>Controlling Interrupt Distribution</title>
</section>
</section>
<section href="ch02.html#LE18698-PARENT" id="LE18698-PARENT">
<title>REACT/pro Frame Scheduler</title>
</section>
<section href="ch02.html#LE42590-PARENT" id="LE42590-PARENT">
<title>Synchronization and Communication</title>
<section href="ch02.html#id5187945" id="id5187945">
<title>Shared Memory Segments</title>
</section>
<section href="ch02.html#LE30650-PARENT" id="LE30650-PARENT">
<title>Semaphores</title>
</section>
<section href="ch02.html#LE22620-PARENT" id="LE22620-PARENT">
<title>Locks</title>
</section>
<section href="ch02.html#id5188385" id="id5188385">
<title>Mutual Exclusion Primitives</title>
</section>
<section href="ch02.html#LE45686-PARENT" id="LE45686-PARENT">
<title>Signals</title>
<section href="ch02.html#id5188553" id="id5188553">
<title>Signal Latency</title>
</section>
<section href="ch02.html#id5188589" id="id5188589">
<title>Signal Families</title>
<table href="ch02.html#id5188635" id="id5188635">
<title>Table 2-1. Signal Handling Interfaces</title>
</table>
</section>
</section>
</section>
<section href="ch02.html#LE85496-PARENT" id="LE85496-PARENT">
<title>Timers and Clocks</title>
<section href="ch02.html#LE59558-PARENT" id="LE59558-PARENT">
<title>Hardware Cycle Counter</title>
</section>
</section>
<section href="ch02.html#LE78556-PARENT" id="LE78556-PARENT">
<title>Interchassis Communication</title>
<section href="ch02.html#id5189333" id="id5189333">
<title>Socket Programming</title>
</section>
<section href="ch02.html#id5189385" id="id5189385">
<title>Message-Passing Interface (MPI)</title>
</section>
<section href="ch02.html#LE32787-PARENT" id="LE32787-PARENT">
<title>Reflective Shared Memory</title>
</section>
<section href="ch02.html#LE53277-PARENT" id="LE53277-PARENT">
<title>External Interrupts</title>
</section>
</section>
</chapter>
<chapter href="ch03.html" id="LE32752-PARENT">
<title>Chapter 3. Controlling CPU Workload</title>
<section href="ch03.html#LE76094-PARENT" id="LE76094-PARENT">
<title>Using Priorities and Scheduling Queues</title>
<section href="ch03.html#LE54745-PARENT" id="LE54745-PARENT">
<title>Scheduling Concepts</title>
<section href="ch03.html#LE52834-PARENT" id="LE52834-PARENT">
<title>Tick Interrupts</title>
</section>
<section href="ch03.html#id5189885" id="id5189885">
<title>Time Slices</title>
</section>
<section href="ch03.html#LE41392-PARENT" id="LE41392-PARENT">
<title>Understanding the Real-Time Priority
 Band</title>
<figure href="ch03.html#id5190077" id="id5190077">
<title>Figure 3-1. Real-Time Priority Band</title>
</figure>
<table href="ch03.html#id5190169" id="id5190169">
<title>Table 3-1. schedctl() Real-Time Priority Range Remapping</title>
</table>
</section>
</section>
<section href="ch03.html#LE25533-PARENT" id="LE25533-PARENT">
<title>Understanding Affinity Scheduling</title>
</section>
<section href="ch03.html#LE86141-PARENT" id="LE86141-PARENT">
<title>Using Gang Scheduling</title>
<example href="ch03.html#LE16911-PARENT" id="LE16911-PARENT">
<title>Example 3-1. Initiating Gang Scheduling </title>
</example>
</section>
<section href="ch03.html#id5190836" id="id5190836">
<title>Changing the Time Slice Duration</title>
<example href="ch03.html#LE12833-PARENT" id="LE12833-PARENT">
<title>Example 3-2. Setting the Time-Slice Length</title>
</example>
</section>
<section href="ch03.html#id5190929" id="id5190929">
<title>Controlling Kernel Threads</title>
</section>
</section>
<section href="ch03.html#LE48058-PARENT" id="LE48058-PARENT">
<title>Minimizing Overhead Work</title>
<section href="ch03.html#LE38943-PARENT" id="LE38943-PARENT">
<title>Assigning the Clock Processor</title>
<example href="ch03.html#LE60468-PARENT" id="LE60468-PARENT">
<title>Example 3-3. Setting the Clock CPU </title>
</example>
</section>
<section href="ch03.html#id5191500" id="id5191500">
<title>Unavoidable Timer Interrupts</title>
</section>
<section href="ch03.html#LE50476-PARENT" id="LE50476-PARENT">
<title>Isolating a CPU from Sprayed Interrupts</title>
</section>
<section href="ch03.html#LE16684-PARENT" id="LE16684-PARENT">
<title>Redirecting Interrupts</title>
</section>
<section href="ch03.html#LE82053-PARENT" id="LE82053-PARENT">
<title>Understanding the Vertical Sync Interrupt</title>
</section>
<section href="ch03.html#LE87243-PARENT" id="LE87243-PARENT">
<title>Restricting a CPU from Scheduled Work</title>
<example href="ch03.html#LE19416-PARENT" id="LE19416-PARENT">
<title>Example 3-4. Number of Processors Available and Total </title>
</example>
<example href="ch03.html#LE18518-PARENT" id="LE18518-PARENT">
<title>Example 3-5. Restricting a CPU </title>
</example>
<section href="ch03.html#LE43268-PARENT" id="LE43268-PARENT">
<title>Assigning Work to a Restricted CPU</title>
<example href="ch03.html#LE61312-PARENT" id="LE61312-PARENT">
<title>Example 3-6. Assigning the Calling Process to a CPU </title>
</example>
</section>
</section>
<section href="ch03.html#LE74709-PARENT" id="LE74709-PARENT">
<title>Isolating a CPU from TLB Interrupts</title>
<section href="ch03.html#id5193419" id="id5193419">
<title>Isolating a CPU When Performer Is Used</title>
</section>
</section>
<section href="ch03.html#LE27459-PARENT" id="LE27459-PARENT">
<title>Making a CPU Nonpreemptive</title>
<example href="ch03.html#LE80538-PARENT" id="LE80538-PARENT">
<title>Example 3-7. Making a CPU nonpreemptive </title>
</example>
</section>
</section>
<section href="ch03.html#LE71892-PARENT" id="LE71892-PARENT">
<title>Minimizing Interrupt Response Time</title>
<section href="ch03.html#LE23937-PARENT" id="LE23937-PARENT">
<title>Maximum Response Time Guarantee</title>
</section>
<section href="ch03.html#LE24810-PARENT" id="LE24810-PARENT">
<title>Components of Interrupt Response Time</title>
<figure href="ch03.html#id5194103" id="id5194103">
<title>Figure 3-2. Components of Interrupt Response Time</title>
</figure>
</section>
<section href="ch03.html#id5194125" id="id5194125">
<title>Hardware Latency</title>
</section>
<section href="ch03.html#id5194212" id="id5194212">
<title>Software Latency</title>
<section href="ch03.html#LE96374-PARENT" id="LE96374-PARENT">
<title>Kernel Critical Sections</title>
</section>
</section>
<section href="ch03.html#LE44094-PARENT" id="LE44094-PARENT">
<title>Device Service Time</title>
</section>
<section href="ch03.html#id5194548" id="id5194548">
<title>Dispatch User Thread</title>
</section>
<section href="ch03.html#id5194567" id="id5194567">
<title>Mode Switch</title>
</section>
<section href="ch03.html#id5194585" id="id5194585">
<title>Minimal Interrupt Response Time</title>
</section>
</section>
</chapter>
<chapter href="ch04.html" id="LE96303-PARENT">
<title>Chapter 4. Using the Frame Scheduler</title>
<section href="ch04.html#LE46755-PARENT" id="LE46755-PARENT">
<title>Frame Scheduler Concepts</title>
<section href="ch04.html#id5194865" id="id5194865">
<title>Frame Scheduler Basics</title>
</section>
<section href="ch04.html#id5194976" id="id5194976">
<title>Thread Programming Models</title>
</section>
<section href="ch04.html#id5195013" id="id5195013">
<title>Frame Scheduling</title>
<figure href="ch04.html#id5195196" id="id5195196">
<title>Figure 4-1. Major and Minor Frames</title>
</figure>
<section href="ch04.html#LE27151-PARENT" id="LE27151-PARENT">
<title>The FRS Controller Thread</title>
</section>
</section>
<section href="ch04.html#LE95148-PARENT" id="LE95148-PARENT">
<title>The Frame Scheduler API</title>
</section>
<section href="ch04.html#id5195768" id="id5195768">
<title>Interrupt Information Templates</title>
<section href="ch04.html#id5195925" id="id5195925">
<title>Library Interface for C Programs</title>
<table href="ch04.html#id5195945" id="id5195945">
<title>Table 4-1. Frame Scheduler Operations</title>
</table>
</section>
<section href="ch04.html#id5197783" id="id5197783">
<title>System Call Interface for Fortran and Ada</title>
<table href="ch04.html#id5197853" id="id5197853">
<title>Table 4-2. Frame Scheduler schedctl() Support</title>
</table>
</section>
</section>
<section href="ch04.html#id5198565" id="id5198565">
<title>Thread Execution</title>
<example href="ch04.html#LE40108-PARENT" id="LE40108-PARENT">
<title>Example 4-1. Skeleton of an Activity Thread </title>
</example>
<example href="ch04.html#LE41040-PARENT" id="LE41040-PARENT">
<title>Example 4-2. Alternate Skeleton of Activity Thread</title>
</example>
</section>
<section href="ch04.html#LE74203-PARENT" id="LE74203-PARENT">
<title>Scheduling Within a Minor Frame</title>
<section href="ch04.html#id5198989" id="id5198989">
<title>Scheduler Flags frs_run and frs_yield</title>
</section>
<section href="ch04.html#id5199087" id="id5199087">
<title>Detecting Overrun and Underrun</title>
</section>
<section href="ch04.html#id5199160" id="id5199160">
<title>Estimating Available Time</title>
</section>
</section>
<section href="ch04.html#id5199220" id="id5199220">
<title>Synchronizing Multiple Schedulers</title>
</section>
<section href="ch04.html#id5199358" id="id5199358">
<title>Starting a Single Scheduler</title>
</section>
<section href="ch04.html#LE71560-PARENT" id="LE71560-PARENT">
<title>Starting Multiple Schedulers</title>
</section>
<section href="ch04.html#id5199558" id="id5199558">
<title>Pausing Frame Schedulers</title>
</section>
<section href="ch04.html#LE44733-PARENT" id="LE44733-PARENT">
<title>Managing Activity Threads</title>
</section>
</section>
<section href="ch04.html#LE12213-PARENT" id="LE12213-PARENT">
<title>Selecting a Time Base</title>
<section href="ch04.html#id5200014" id="id5200014">
<title>On-Chip Timer Interrupt</title>
</section>
<section href="ch04.html#id5200077" id="id5200077">
<title>High-Resolution Timer</title>
</section>
<section href="ch04.html#LE84592-PARENT" id="LE84592-PARENT">
<title>Vertical Sync Interrupt</title>
</section>
<section href="ch04.html#LE21988-PARENT" id="LE21988-PARENT">
<title>External Interrupts</title>
</section>
<section href="ch04.html#LE25121-PARENT" id="LE25121-PARENT">
<title>Device Driver Interrupt</title>
</section>
<section href="ch04.html#LE35769-PARENT" id="LE35769-PARENT">
<title>Software Interrupt</title>
</section>
<section href="ch04.html#id5200620" id="id5200620">
<title>User-Level Interrupts</title>
</section>
</section>
<section href="ch04.html#LE97767-PARENT" id="LE97767-PARENT">
<title>Using the Scheduling Disciplines</title>
<section href="ch04.html#id5200765" id="id5200765">
<title>Real-Time Discipline</title>
</section>
<section href="ch04.html#id5200946" id="id5200946">
<title>Background Discipline</title>
</section>
<section href="ch04.html#id5200985" id="id5200985">
<title>Underrunable Discipline</title>
</section>
<section href="ch04.html#id5201041" id="id5201041">
<title>Overrunnable Discipline</title>
</section>
<section href="ch04.html#id5201142" id="id5201142">
<title>Continuable Discipline</title>
</section>
<section href="ch04.html#LE16055-PARENT" id="LE16055-PARENT">
<title>Using Multiple Consecutive Minor Frames</title>
</section>
</section>
<section href="ch04.html#LE21771-PARENT" id="LE21771-PARENT">
<title>Designing an Application for the Frame Scheduler</title>
</section>
<section href="ch04.html#LE37845-PARENT" id="LE37845-PARENT">
<title>Preparing the System</title>
</section>
<section href="ch04.html#LE48091-PARENT" id="LE48091-PARENT">
<title>Implementing a Single Frame Scheduler</title>
</section>
<section href="ch04.html#LE82868-PARENT" id="LE82868-PARENT">
<title>Implementing Synchronized Schedulers</title>
<section href="ch04.html#id5202117" id="id5202117">
<title>Synchronized Scheduler Concepts</title>
</section>
<section href="ch04.html#id5202199" id="id5202199">
<title>Implementing a Master Controller Thread</title>
</section>
<section href="ch04.html#id5202436" id="id5202436">
<title>Implementing Slave Controller Threads</title>
</section>
</section>
<section href="ch04.html#LE43451-PARENT" id="LE43451-PARENT">
<title>Handling Frame Scheduler Exceptions</title>
<section href="ch04.html#id5202684" id="id5202684">
<title>Exception Types</title>
</section>
<section href="ch04.html#id5202753" id="id5202753">
<title>Exception Handling Policies</title>
<section href="ch04.html#id5202808" id="id5202808">
<title>Injecting a Repeat Frame</title>
</section>
<section href="ch04.html#id5202828" id="id5202828">
<title>Extending the Current Frame</title>
</section>
<section href="ch04.html#id5202864" id="id5202864">
<title>Dealing With Multiple Exceptions</title>
</section>
</section>
<section href="ch04.html#LE51755-PARENT" id="LE51755-PARENT">
<title>Setting Exception Policies</title>
<example href="ch04.html#LE97483-PARENT" id="LE97483-PARENT">
<title>Example 4-3. Function to Set INJECTFRAME Exception Policy</title>
</example>
<example href="ch04.html#LE94737-PARENT" id="LE94737-PARENT">
<title>Example 4-4. Function to Set STRETCH Exception Policy</title>
</example>
</section>
<section href="ch04.html#id5203159" id="id5203159">
<title>Querying Counts of Exceptions</title>
<example href="ch04.html#LE48489-PARENT" id="LE48489-PARENT">
<title>Example 4-5. Function to Return a Sum of Exception Counts (pthread Model)</title>
</example>
</section>
</section>
<section href="ch04.html#LE72300-PARENT" id="LE72300-PARENT">
<title>Using Signals Under the Frame Scheduler</title>
<section href="ch04.html#LE54747-PARENT" id="LE54747-PARENT">
<title>Signal Delivery and Latency</title>
</section>
<section href="ch04.html#id5203500" id="id5203500">
<title>Handling Signals in the FRS Controller</title>
</section>
<section href="ch04.html#LE88749-PARENT" id="LE88749-PARENT">
<title>Handling Signals in an Activity Thread</title>
</section>
<section href="ch04.html#LE54102-PARENT" id="LE54102-PARENT">
<title>Setting Frame Scheduler Signals</title>
<table href="ch04.html#id5203834" id="id5203834">
<title>Table 4-3. Signal Numbers Passed in frs_signal_info_t</title>
</table>
<example href="ch04.html#LE72819-PARENT" id="LE72819-PARENT">
<title>Example 4-6. Function to Set Frame Scheduler Signals</title>
</example>
</section>
<section href="ch04.html#LE43574-PARENT" id="LE43574-PARENT">
<title>Sequence Error</title>
</section>
</section>
<section href="ch04.html#LE55284-PARENT" id="LE55284-PARENT">
<title>Using Timers with the Frame Scheduler</title>
<example href="ch04.html#LE24592-PARENT" id="LE24592-PARENT">
<title>Example 4-7. Minimal Activity Process as a Timer</title>
</example>
</section>
<section href="ch04.html#LE38756-PARENT" id="LE38756-PARENT">
<title>FRS Kernel-Level Device Driver Interface</title>
<section href="ch04.html#id5204400" id="id5204400">
<title>Device Driver Overview</title>
</section>
<section href="ch04.html#LE76652-PARENT" id="LE76652-PARENT">
<title>Registering the Initialization and Termination Functions</title>
<example href="ch04.html#LE10167-PARENT" id="LE10167-PARENT">
<title>Example 4-8. Exporting Device Driver Entry Points</title>
</example>
</section>
<section href="ch04.html#id5204676" id="id5204676">
<title>Frame Scheduler Initialization Function</title>
<example href="ch04.html#LE23314-PARENT" id="LE23314-PARENT">
<title>Example 4-9. Device Driver Initialization Function</title>
</example>
</section>
<section href="ch04.html#id5204906" id="id5204906">
<title>Frame Scheduler Termination Function</title>
<example href="ch04.html#LE69181-PARENT" id="LE69181-PARENT">
<title>Example 4-10. Device Driver Termination Function</title>
</example>
</section>
<section href="ch04.html#LE38389-PARENT" id="LE38389-PARENT">
<title>Generating Interrupts</title>
<example href="ch04.html#LE68912-PARENT" id="LE68912-PARENT">
<title>Example 4-11. Generating an Interrupt From a Device Driver</title>
</example>
<example href="ch04.html#LE34698-PARENT" id="LE34698-PARENT">
<title>Example 4-12. Registering a Nonthreaded Interrupt Handler</title>
</example>
</section>
</section>
</chapter>
<chapter href="ch05.html" id="LE36019-PARENT">
<title>Chapter 5. Optimizing Disk I/O for a Real-Time Program</title>
<section href="ch05.html#LE13930-PARENT" id="LE13930-PARENT">
<title>Memory-Mapped I/O</title>
</section>
<section href="ch05.html#LE50967-PARENT" id="LE50967-PARENT">
<title>Asynchronous I/O</title>
<section href="ch05.html#id5205464" id="id5205464">
<title>Conventional Synchronous I/O</title>
</section>
<section href="ch05.html#LE73732-PARENT" id="LE73732-PARENT">
<title>Asynchronous I/O Basics</title>
</section>
</section>
<section href="ch05.html#LE14806-PARENT" id="LE14806-PARENT">
<title>Guaranteed-Rate I/O (GRIO)</title>
</section>
</chapter>
<chapter href="ch06.html" id="LE93712-PARENT">
<title>Chapter 6. Managing Device Interactions</title>
<section href="ch06.html#LE85724-PARENT" id="LE85724-PARENT">
<title>Device Drivers</title>
<section href="ch06.html#id5205875" id="id5205875">
<title>How Devices Are Defined</title>
</section>
<section href="ch06.html#id5205954" id="id5205954">
<title>How Devices Are Used</title>
<section href="ch06.html#id5206036" id="id5206036">
<title>Device Driver Entry Points</title>
</section>
</section>
<section href="ch06.html#id5206409" id="id5206409">
<title>Taking Control of Devices</title>
</section>
</section>
<section href="ch06.html#LE94299-PARENT" id="LE94299-PARENT">
<title>SCSI Devices</title>
<section href="ch06.html#id5206594" id="id5206594">
<title>SCSI Adapter Support</title>
</section>
<section href="ch06.html#id5206625" id="id5206625">
<title>System Disk Device Driver</title>
</section>
<section href="ch06.html#id5206665" id="id5206665">
<title>System Tape Device Driver</title>
</section>
<section href="ch06.html#LE10662-PARENT" id="LE10662-PARENT">
<title>Generic SCSI Device Driver</title>
</section>
<section href="ch06.html#id5207033" id="id5207033">
<title>CD-ROM and DAT Audio Libraries</title>
</section>
</section>
<section href="ch06.html#id5207109" id="id5207109">
<title>The PCI Bus</title>
<example href="ch06.html#LE16688-PARENT" id="LE16688-PARENT">
<title>Example 6-1. Memory Mapping With pciba</title>
</example>
</section>
<section href="ch06.html#LE25650-PARENT" id="LE25650-PARENT">
<title>The VME Bus</title>
<section href="ch06.html#id5207319" id="id5207319">
<title>Challenge an Onyx Hardware Nomenclature</title>
<figure href="ch06.html#id5207439" id="id5207439">
<title>Figure 6-1. Multiprocessor Challenge Data Path Components</title>
</figure>
</section>
<section href="ch06.html#id5207462" id="id5207462">
<title>VME Bus Attachments</title>
<table href="ch06.html#id5207493" id="id5207493">
<title>Table 6-1. Multiprocessor Challenge VME Cages and Slots</title>
</table>
<table href="ch06.html#id5207780" id="id5207780">
<title>Table 6-2. Power Channel-2 and VME bus Configurations</title>
</table>
</section>
<section href="ch06.html#id5208098" id="id5208098">
<title>VME Address Space Mapping</title>
<section href="ch06.html#id5208212" id="id5208212">
<title>PIO Address Space Mapping</title>
</section>
<section href="ch06.html#LE74488-PARENT" id="LE74488-PARENT">
<title>DMA Mapping</title>
</section>
</section>
<section href="ch06.html#LE78134-PARENT" id="LE78134-PARENT">
<title>Program Access to the VME Bus</title>
<section href="ch06.html#LE50284-PARENT" id="LE50284-PARENT">
<title>PIO Access</title>
<table href="ch06.html#id5208502" id="id5208502">
<title>Table 6-3. VME Bus PIO Bandwidth 
</title>
</table>
</section>
<section href="ch06.html#LE16935-PARENT" id="LE16935-PARENT">
<title>User-Level Interrupt Handling</title>
</section>
<section href="ch06.html#LE42290-PARENT" id="LE42290-PARENT">
<title>DMA Access to Master Devices</title>
<table href="ch06.html#id5208876" id="id5208876">
<title>Table 6-4. VME Bus Bandwidth, VME Master Controlling DMA</title>
</table>
</section>
<section href="ch06.html#LE81572-PARENT" id="LE81572-PARENT">
<title>DMA Engine Access to Slave Devices</title>
<table href="ch06.html#id5209533" id="id5209533">
<title>Table 6-5. VME Bus Bandwidth, DMA Engine, D32 Transfer (Challenge/Onyx Systems)</title>
</table>
<table href="ch06.html#id5209922" id="id5209922">
<title>Table 6-6. VME Bus Bandwidth, DMA Engine, D32 Transfer (Origin/Onyx 2 Systems)</title>
</table>
</section>
</section>
</section>
<section href="ch06.html#LE73027-PARENT" id="LE73027-PARENT">
<title>Serial Ports</title>
</section>
<section href="ch06.html#LE78160-PARENT" id="LE78160-PARENT">
<title>External Interrupts</title>
</section>
</chapter>
<chapter href="ch07.html" id="LE13812-PARENT">
<title>Chapter 7. Managing User-Level Interrupts</title>
<figure href="ch07.html#id5210848" id="id5210848">
<title>Figure 7-1. ULI Functional Overview</title>
</figure>
<section href="ch07.html#id5210886" id="id5210886">
<title>Overview of ULI</title>
<section href="ch07.html#id5210953" id="id5210953">
<title>The ULI Handler </title>
</section>
<section href="ch07.html#id5210999" id="id5210999">
<title>Restrictions on the ULI Handler</title>
<figure href="ch07.html#id5211163" id="id5211163">
<title>Figure 7-2. ULI Handler Functions</title>
</figure>
</section>
<section href="ch07.html#id5211186" id="id5211186">
<title>Planning for Concurrency</title>
<section href="ch07.html#id5211200" id="id5211200">
<title>Debugging With Interrupts</title>
</section>
<section href="ch07.html#id5211230" id="id5211230">
<title>Declaring Global Variables</title>
</section>
</section>
<section href="ch07.html#id5211300" id="id5211300">
<title>Using Multiple Devices</title>
</section>
</section>
<section href="ch07.html#id5211379" id="id5211379">
<title>Setting Up</title>
<section href="ch07.html#id5211492" id="id5211492">
<title>Opening the Device Special File</title>
</section>
<section href="ch07.html#id5211651" id="id5211651">
<title>Locking the Program Address Space</title>
</section>
<section href="ch07.html#id5211843" id="id5211843">
<title>Registering the Interrupt Handler</title>
<section href="ch07.html#LE53522-PARENT" id="LE53522-PARENT">
<title>Registering an External Interrupt Handler</title>
</section>
<section href="ch07.html#id5212168" id="id5212168">
<title>Registering a VME Interrupt Handler</title>
</section>
<section href="ch07.html#id5212298" id="id5212298">
<title>Registering a PCI Interrupt Handler</title>
</section>
</section>
<section href="ch07.html#LE99742-PARENT" id="LE99742-PARENT">
<title>Interacting With the Handler</title>
<section href="ch07.html#id5212645" id="id5212645">
<title>Achieving Mutual Exclusion</title>
</section>
</section>
</section>
<section href="ch07.html#id5212743" id="id5212743">
<title>Sample Programs</title>
<example href="ch07.html#LE16544-PARENT" id="LE16544-PARENT">
<title>Example 7-1. Hypothetical PCI ULI Program</title>
</example>
<example href="ch07.html#LE26046-PARENT" id="LE26046-PARENT">
<title>Example 7-2. Hypothetical External Interrupt ULI Program</title>
</example>
</section>
</chapter>
<appendix href="apa.html" id="LE15237-PARENT">
<title>Appendix A. Sample Programs</title>
<table href="apa.html#id5213209" id="id5213209">
<title>Table A-1. Summary of Frame Scheduler Example Programs</title>
</table>
<section href="apa.html#LE29372-PARENT" id="LE29372-PARENT">
<title>Basic Example</title>
<section href="apa.html#id5213515" id="id5213515">
<title>Real-Time Application Specification</title>
</section>
<section href="apa.html#id5213543" id="id5213543">
<title>Frame Scheduler Design</title>
</section>
</section>
<section href="apa.html#LE83528-PARENT" id="LE83528-PARENT">
<title>Example of Scheduling Separate Programs</title>
</section>
<section href="apa.html#LE24688-PARENT" id="LE24688-PARENT">
<title>Examples of Multiple Synchronized Schedulers</title>
<section href="apa.html#id5214176" id="id5214176">
<title>Example of Device Driver</title>
</section>
<section href="apa.html#id5214245" id="id5214245">
<title>Examples of a 60 Hz Frame Rate</title>
</section>
<section href="apa.html#id5214311" id="id5214311">
<title>Example of Managing Lightweight Processes</title>
</section>
<section href="apa.html#LE31744-PARENT" id="LE31744-PARENT">
<title>The simple_pt Pthreads Program</title>
</section>
</section>
</appendix>
<glossary href="go01.html" id="id5214647">
<title>Glossary</title>
</glossary>
<index href="ix01.html" id="sgi-index">
<title>Index</title>
</index>
</book>
</toc>
