This chapter describes general VME interface board operating information. It contains the following sections:
“VME Interface Board Description” provides a physical description of the VME interface board.
“VME LED Functionality” describes the VME interface board LEDs.
“VME Interface Board Jumper Settings” describes the jumper settings required for Origin200 GIGAchannel server operation.
“VME System Controller Information” describes basic VME system controller card functions.
“VME Interface Board Operation” describes basic VME interface board operations.
The VME interface board is available in two sizes (6U and 9U), depending on the VME chassis size (see Figure 4-1). It functions as the System Controller card between the VME chassis and the Silicon Graphics host system. The VME adapter board must always be installed in VME chassis slot 1.
The VME interface board has eight LEDs located on the front panel that indicate VME system operating modes (see Figure 4-2 and Table 4-1). Note that LED0, LED1, LED2, and LED3 are not used.
Table 4-1. VME Board LED Functions
LED | Function |
|---|---|
LED 0 (Yellow) | On, but not used at this time. |
LED 1 (Yellow) | On, but not used at this time. |
LED 2 (Yellow) | Not used at this time. |
LED 3 (Yellow) | Not used at this time. |
3.3 V OK (Green) | Displays status of 3.3 voltage board level. On indicates board 3.3 voltage is OK. Off indicates no voltage or voltage out of range. (On during normal operation.) |
LINK OK (Green) | Monitors the voltage link connection between the VME interface board and VME XIO board. On indicates link is OK. Off or flashing indicates linkage problem. (On during normal operation.) |
1.7 V OK (Green) | Displays status of voltage board level. On indicates board 1.7 voltage is OK. Off indicates no voltage or voltage out of range. (On during normal operation.) |
2.4 OK (Green) | Displays status of voltage board level. On indicates board 2.4 voltage is OK. Off indicates no voltage or voltage out of range. (On during normal operation.) |
The VME interface board is shipped from the factory with the oscillator jumper settings pre-configured for use in Origin2000 and Onyx2 systems. When using the VME interface board in an Origin200 GIGAchannel server, the oscillator jumper settings must be changed to 360 MHz operation.
Use the following steps to set the 6U VME interface board oscillator jumper settings to 360 MHz operation (see Figure 4-3).
Use the following steps to set the 9U VME interface board oscillator jumper settings to 360 MHz operation (see Figure 4-4).
The VME interface board functions as the System Controller on the VME bus chassis to which it is attached. As the System Controller, the VME interface board provides the following functions:
bus arbitration
interrupt acknowledgment (IACK)
system clock (SYSCLK)
bus timer
 | Note: The System Controller functions are sometimes referred to as slot 1 functions. |
As VME bus arbitrator, the VME interface board provides fixed priority arbitration. The fixed priority method arbitrates bus requests in the following order: BR3, BR2, BR1 then BR0 (by convention, BR3 is the highest priority request). One bus grant is issued to the highest requesting device. If a bus request of higher priority than the current bus owner is asserted, the VME interface board asserts BCLR until the current owner releases the bus.
Additionally, the VME interface board bus arbitration logic provides a timeout if a requester does not assert the BBSY within 16 microseconds after the appropriate Bus Grant signal (BGxOUT) has been asserted.
The VME interface board will complete interrupt acknowledge cycles only to Interrupt Priority Levels (IPLs) identified with VECTOR statements in the irix.sm file, or with those explicitly identified in calls to vmeio_intr_alloc() calls. Once the IACK cycle is complete, the IRIX device driver handling the interrupt executes on one of the CPUs of the Origin or Onyx2 system. This functionality is similar to the CHALLENGE or Onyx VME bus interface. The interrupt status/ID (interrupt vector) returned by the interrupting device during the IACK cycle must be 8 bits.
All seven VME interrupt request levels (IRQ1-IRQ7) are supported by the VME interface board. All seven VME interrupt request levels are also routable through the DEVICE_ADMIN directive found in the /var/sysgen/system/irix.sm file. (Up to six of the seven IPL levels may be routed at one time.)
Only Release On Acknowledge (ROAK) interrupting devices are supported, because the interrupt acknowledge cycle is performed independently of the Origin or Onyx2 CPUs (Release On Register Access [RORA] devices are not supported).
The VME bus timer asserts BERR if a VME bus transaction times out (indicated by one of the VME bus data strobes remaining asserted beyond the timeout period). The VME bus time-out period is set to 64 microseconds.
The VME interface board can function as either a master (initiating I/O requests on the bus) or as a slave (responding to I/O requests on the bus from other masters).
As a VME bus master, the VME interface board can access A16, A24, and A32 address space in both supervisory and non-privileged modes. Data accesses via the CPUs (for example, through Programmed IO) can be for D8, D16, and D32 sizes. Data accesses via the VME interface board's DMA engine can be for D8, D16, D32, and D64 sizes. RMW cycles, address-only cycles, tri-byte accesses or non-aligned data accesses are not supported. The VME interface board makes all VME bus requests at bus request level 3 (BR3)-the highest priority level. Bus requests are made by the VME interface board to initiate interrupts, DMA requests, and PIO requests. Bus requests are made regardless of the state of the bus request lines on the VME bus and released in a release-when-done (RWD) fashion (the same policy as the CHALLENGE and Onyx VME interface). In addition, the VME interface board does not monitor BCLR, so its ownership of the VME bus is not affected by other devices asserting BCLR.
As a VME bus slave, the VME interface board accepts accesses to A24 and A32 address space in both supervisory and non-privileged modes. Data accesses from third-party VME devices can be D8, D16, D32, and D64 sizes. RMW cycles, address-only cycles, tri-byte accesses, or non-aligned data accesses are not supported. In order for third-party VME devices to access Onyx2 or Origin memory address space directly, a valid DMA map must exist. This is true even if access to the memory is done only through programmed I/O (PIO).
The VME interface board performs write posting as a VME slave, using its 64-bit, 32-entry deep FIFO. This enables VME bus writes to complete much faster, freeing up the VME bus for other transactions. Similarly, block reads (BLT or MBLT) presented to the VME interface board are prefetched into another 64-bit, 32-entry deep FIFO. In this fashion, the Origin or Onyx2 system can burst data to the VME bus much more quicker, avoiding waiting for relatively slow data cycles on the VME bus. When acting as slave, the VME interface board actively drives DTACK to its negated level when it releases the VME bus. This feature is commonly referred to as DTACK rescinding.
The CHALLENGE or Onyx VME interface permitted VME block transfers to occur across 256-byte boundaries for the D32 transfer and 2048-byte boundaries for the D64 transfer. This was in violation of revision D of the VME specification and is not permitted with the XIO-VME interface. Some CHALLENGE and Onyx device drivers and/or third-party VME hardware and software may need modification if the block transfers were performed beyond these 256/2048-byte boundaries.