The DVP2 minimizes latency to video data. Typically, there is less than one horizontal period of latency in the video data. The exact latency depends on the particular video format and the pixel clock speed. There are three distinct “break-points”: 2.5 to 60 Mpix/sec, 60 to 120 Mpixels/sec, and 120 to 230 Mpixels/sec. The highest clock rate adds 3 pixel clocks of delay, the mid-range adds a total of 2 pixel clocks of delay, and the low range adds no delay. In all three cases, the relationship of CBLANK_{H,L} to video data is constant. (See “Timing Signals” for more information.) The latency is negligible in most applications. Digital video data on the DVP2 appears in the same frame as video on the analog channels.

The DVP2 physical interface consists of a single connector located on the DG5 board front connector panel organized as 45 differential signal pairs. These signal pairs consist of the following:

A CrayLink cable connects the digital video stream from the Onyx2 InfiniteReality graphics system to a video peripheral board located outside the Onyx2 chassis in a customer-supplied chassis.

The Digital Video Port option is a board set consisting of a DG5 board with an attached DVP2 daughterboard. This DVP2 daughterboard implements a user-programmable digital video channel similar to the other analog video channels of the Onyx2 InfiniteReality graphics subsystem. Figure 1-1 shows the block diagram of the DVP2 daughterboard.

The receiver connector on the customer equipment must be mechanically and electrically compatible with the following connector: 3M part number 102A0-5242VC. There should be no built-in EMI filtering because of the deleterious effect it would have on electrical performance. (See Figure 1-2 for the component-side connector footprint.)

There are 72 video data signals, which comprise 36 differential signal pairs. These are comprised of three color components of 12 bits each: (RED_OUT_{H,L}[11:0], GREEN_OUT_{H,L}[11:0], BLUE_OUT_{H,L}[11:0]). The InfiniteReality DVP2 interface does not include the Alpha channel.

This document uses the following video data signal naming convention: ColorComponentName_OUT_SignalPolarity[SignificantBit]. The last digit of the signal name indicates the binary significance of the digital color component. For example, the most significant bit of the positive-logic version green component is GREEN_OUT_H[11].

To control in-flight skew between clock and data caused by nonuniform group delay in the cable, it is important to carefully match the spectral characteristics of the clocks to the data transmitted on the DVP2 interface. This is accomplished by transmitting an in-phase and a quadrature-phase version of the pixel clock, divided by 2. (See Figure 1-4 for Silicon Graphics recommendations for recovering a full-speed pixel clock on the receiver. See Figure 1-5 for Timing Diagram information.)

CBLANK_{H,L}, CSYNC_{H,L}, VSYNC_{H,L}, FIELD_{H,L} indicate the structure of the video raster being transmitted by the DVP2 interface. These signals are user-programmable via the Video Format Compiler. (For more information, see the InfiniteReality Video Format Compiler Programming Guide, part number 007-3402-001). CBLANK serves as an indicator of active video. It has a fixed, non-programmable, 3-pixel clock skew with respect to video. CBLANK will transition active/inactive 3 pixel clocks (3 edges of CLK_2_QUAD) before video data. The skew allows for easy implementation of control circuits in the receiver. FIELD_{H,L} indicates the field that is currently being transmitted. For non-interlaced video formats, FIELD_H is always inactive (low). For interlaced formats, FIELD_H is always active (high) throughout the second field of the frame.

The VOC_SWAP signal indicates the first frame of video that occurs after the framebuffer memory has been swapped. This is the default semantics of this signal. VOC_SWAP is actually a catch-all signal. It may be statically programmed to send any one of the following 6 video signals:

For more information, contact Silicon Graphics technical support or your local service provider.

These signals are reserved for future development of the DVP2 interface. The current implementation always asserts these two signal pairs as LOW.

The DVP2 interface uses differential, 5-volt positive-ECL (5V-PECL) signalling, which provides speed and the ability to correctly terminate transmission lines. However, because of the circuit configuration of ECL driver circuits, damage can result if the drivers attempt to drive powered-down receivers. For this reason, the DVP2 interface expects the receiving equipment to send a voltage equal to the power supply voltage of the 5V-PECL clock and data receiver circuits. (The voltage should be current-limited for safety considerations.) Under normal operating conditions, this pin should provide the DVP2 board with 0.1 mA of 4.6 V to 5.8 V. If PWR_GOOD is not in this range (with respect to ground on the DVP2 board), the DVP2 PECL circuitry will be powered down to avoid damage.

These signals support the VESA DDC standard for communicating with video peripherals (monitors, projectors, LCD panels, etc.) using the Phillips I²C standard. These signals are not 5V_PECL signals. I2C_DATA is open-collector, 5V-TTL. I2C_CLOCK is 5V-TTL. The DVP2 board implements these signals using the Phillips PFC8584 I²C Controller. Phillips' application literature has more information about I²C and this controller chip. Unless you are designing equipment that supports the VESA DDC standard, disregard these signals and make no connection to them. (For more information, contact Silicon Graphics technical support or your local service provider.)

The video data and control signals are transmitted from MC100E151 registers clocked by the rising edge of pixel clock. The data signals must be terminated at the receiver with the Thevinin-equivalent network shown in Figure 1-3. The DVP2 interface is a point-to-point interface.

DVP2 pixel clock can be programmed to operate between 2.5 MHz and 175 MHz, allowing the DVP2 interface to support video formats between 2.5 and 175 Mpix/sec. (The DVP2 board was designed for a maximum operating rate of 260 Mpixels/sec, but is not guaranteed beyond 175 Mpix/sec in the Onyx2 InfiniteReality graphics system.) For video formats with clock rates higher than 220 Mpix/sec, the system software automatically uses the high-speed clock. This function is controlled with IRcombine. However, note that the guaranteed rate is still 175 Mpix/sec. Contact Silicon Graphics if your application requirements exceed 175 Mpixels/sec.

Over most of the DVP2's operating range, clock skew is an important consideration in the transmission of pixel clock to the video option board and distributing it to the video option board. Because of its wide operating limits, phase-locked-loop techniques are unsuitable for receiving the clocks on the DVP2 interface. Figure 1-4 shows the circuit recommended by Silicon Graphics for receiving and regenerating a full-speed pixel clock, the method of distributing it, and the recommended circuits for receiving DVP2 video data. The recommended data receiver is a Motorola MC100E452. The recommended clock receiver is a Synergy Semiconductor SY100EL16A.

When the external DVP2 interface cable is not in place, the data drivers are powered down to save power and minimize EMI interference to other equipment. 5V-PECL signals have lower emissions than CMOS or TTL signals. Each differential pair in the external cable is individually shielded with foil. In addition, the entire cable is shielded with a braided shield. The external shield of the DVP2 cable must be tied directly to chassis ground on both the Silicon Graphics logic cabinet and the customer's chassis.

Chassis grounds (on the Onyx2 chassis and the customer equipment) must be at the same potentials, supplied from the same AC mains and ground. PWR_GOOD is likely to be out of spec if there is much difference in ground potential between the two equipment chassis, resulting in a shutdown of the DVP2 interface to prevent equipment damage. (See “Receiver Power Indicator (PWR_GOOD)” for more information.) Both chassis should be supplied from the same AC electrical source in order to minimize ground differentials between chassis.

The branch circuit wiring should be provided with an insulated grounding conductor that is identical in size, insulation material, and thickness to the earthed and unearthed branch-circuit supply conductors. The grounding conductor should be green, with or without one or more yellow stripes. This grounding or earthing conductor should be connected to earth at the service equipment or, if supplied by a separately derived system, at the supply transformer or motor-generated set. The power receptacles in the vicinity of the systems should all be of an earthing type, and the grounding or earthing conductors serving these receptacles should be connected to earth at the service equipment.

Table 1-1 shows the signals on the DVIO connector.

Because of the construction of the external cable, the pinout is reversed on the receiver connector. Table 1-2 shows the pinout of the receiver connector.