List of Figures

| Table of Contents | List of Figures | List of Examples | List of Tables |

Figure 2-1. Links Between Bricks

Figure 2-2. SC-brick Block Diagram

Figure 2-3. IX-brick (PX-brick with BaseIO Card)

Figure 2-4. PX-brick - PCI-X Expansion Brick

Figure 2-5. Address Decoding for Physical Memory Access

Figure 2-6. Bit Values for Global MMR Space

Figure 2-7. Bit Values for AMO Space

Figure 2-8. SHub Physical Address Map

Figure 2-9. Device Access through a Bus Adapter

Figure 2-10. CPU Access to Memory

Figure 2-11. CPU Access to Device Registers (Programmable I/O)

Figure 2-12. Device Access to Memory

Figure 3-1. PX-brick with BaseIO

Figure 3-2. PX-brick PCI-X Expansion

Figure 3-3. PCI-X Implementation

Figure 5-1. Physical Address Components

Figure 6-1. PCI-X Configuration Space

Figure 7-1. PIO Address Format

Figure 7-2. PIO to a Local PCI-X Device

Figure 7-3. PIO to a Remote PCI-X Device

Figure 7-4. PIO Address from the CPU

Figure 9-1. DMA to Memory on A Local Node

Figure 9-2. DMA to Memory on A Remote Node

Figure 9-3. PCI Direct Mapped Register (one per PCI bridge)

Figure 9-4. 32-bit Direct Mapped Address As Returned by the System

Figure 9-5. 50-bit System Memory Address

Figure 9-6. 32-bit DMA Mapped Address

Figure 9-7. 64-bit DMA Mapped Address

Figure A-1. Release Semantics One-Directional Fence

Figure A-2. Acquire Semantics One-Directional Fence

Figure A-3. Two-dimensional Memory Fence (mf)