KA820/KA825 Processor Technical Manual

Company:Digital Equipment Corporation
Part:EK-KA820-TM-003
Date:1987-04
Keywords:VAX 8250 8350

Table of Contents

  • Chapter 1 Introduction to the KA820 Module
    • 1.1 KA820 Functional Sections
      • 1.1.1 CPU Section
      • 1.1.2 VAXBI Interface Section
      • 1.1.3 Port Controller and PCI Bus Devices Section
    • 1.2 Customer Options
    • 1.3 VAXBI Overview
      • 1.3.1 VAXBI Addressing
      • 1.3.2 VAXBI Timing and Arbitration
    • 1.4 KA820 Module Layout
    • 1.5 Power Requirements
    • 1.6 Environmental Requirements
  • Chapter 2 KA820 Module Detailed Description
    • 2.1 CPU Section
      • 2.1.1 I/E Chip Functions
      • 2.1.2 M Chip, BTB, and Cache Functions
        • 2.1.2.1 BTB (Backup Translation Buffer)
        • 2.1.2.2 Cache
        • 2.1.2.3 Internal Processor Registers
        • 2.1.2.4 Serial-Line Units
      • 2.1.3 F Chip Functions
      • 2.1.4 Communication between the Processor Chip Set and the VAXBI Bus
      • 2.1.5 Control-Store Operation
    • 2.2 VAXBI Interface
      • 2.2.1 VAXBI Address Space
      • 2.2.2 KA820 Registers Accessible to Other VAXBI Nodes
      • 2.2.3 VAXBI Transactions
        • 2.2.3.1 KA820-Initiated Transactions
        • 2.2.3.2 KA820 Slave Responses
        • 2.2.3.3 Device Interrupt Sequence
    • 2.3 Port Controller and PCI Devices
      • 2.3.1 PCI Bus Addressing
      • 2.3.2 EEPROM Functions
      • 2.3.3 Watch Chip Interface
      • 2.3.4 RCX50 Controller Interface
  • Chapter 3 Sequences and Options on Power-Up
    • 3.1 Power-Up Sequence and Related Signals and Jumpers
    • 3.2 Self-Test
    • 3.3 Initialization
      • 3.3.1 Power-Up Initialization
      • 3.3.2 Processor Initialization
      • 3.3.3 System Initialization
    • 3.4 Restart and Bootstrap
      • 3.4.1 Restart Function (Warm Start)
      • 3.4.2 Bootstrap Function (Cold Start)
        • 3.4.2.1 EEPROM and Boot RAM Bootstrap Considerations
        • 3.4.2.2 Software Responsibilities in the Bootstrap
        • 3.4.2.3 Loading Secondary Control-Store Patches
    • 3.5 Sample Multiprocessor Configuration Start Sequence
  • Chapter 4 Console Functions
    • 4.1 Console States
    • 4.2 Console Entry
      • 4.2.1 Halt Codes
    • 4.3 Console Commands
      • 4.3.1 Change Console Baud Rate Command (BREAK)
      • 4.3.2 Boot Command (B)
      • 4.3.3 Continue Command (C)
      • 4.3.4 Deposit and Examine Commands (D and E)
      • 4.3.5 Halt Command (H)
      • 4.3.6 Initialize Command (I)
      • 4.3.7 Next Command (N)
      • 4.3.8 Start Command (S)
      • 4.3.9 Test Command (T)
      • 4.3.10 Test with Menu Command (T/M)
      • 4.3.11 Binary Load and Unload Command (X)
      • 4.3.12 VAXBI Forward Command (Z)
      • 4.3.13 Console Comment Command (!)
      • 4.3.14 Enter Console Mode Command (<CTRL/P>)
      • 4.3.15 Forward Next Character Command (<ESC>)
      • 4.3.16 Stop Console Output Command (<CTRL/S>)
      • 4.3.17 Restart Console Output Command (<CTRL/Q>)
      • 4.3.18 Abort Command Line Command (<CTRL/U>)
    • 4.4 Console Error Codes
    • 4.5 Loading Control-Store Patches from the Console
    • 4.6 Logical Console Operation
  • Chapter 5 Handling Exceptions and Interrupts
    • 5.1 System Control Block
    • 5.2 Machine-Check Exceptions
      • 5.2.1 Machine-Check Stack
        • 5.2.1.1 Byte Count, (SP)
        • 5.2.1.2 Parameter 1, (SP) + 8, MTEMPB Register
        • 5.2.1.3 Virtual Address Register, (SP) + C, MTEMP13 Register
        • 5.2.1.4 Virtual Address Prime Register, (SP) + 10, MTEMP.PSL.TEMP Register
        • 5.2.1.5 Memory Address Register, (SP) + 14, MTEMP9 Register
        • 5.2.1.6 Status Word, (SP) + 18, MTEMPC Register
        • 5.2.1.7 Program Counter at Failure, (SP) + 1C
        • 5.2.1.8 MicroPC at Failure, (SP) + 20 (hex)
        • 5.2.1.9 Current Program Counter, (SP) + 24 (hex)
        • 5.2.1.10 Current Processor Status Longword, (SP) + 28 (hex)
    • 5.3 CPU Double-Error Halt Considerations
    • 5.4 Power-Up and Console Mode Errors
  • Chapter 6 Dedicated I/O and Memory Devices
    • 6.1 Serial-Line Units
      • 6.1.1 Receive Control and Status Registers (Read/Write)
        • 6.1.1.1 Bit <12> LP (Loopback Enable, Read/Write)
        • 6.1.1.2 Bit <7> DON (Done, Read Only)
        • 6.1.1.3 Bit <6> Interrupt Enable (Read/Write)
      • 6.1.2 Receive Data Buffer Registers (Read Only)
        • 6.1.2.1 Bit <15> ERR (Error on Received Character, Read Only)
        • 6.1.2.2 Bit <14> BRK (Break, Read Only)
        • 6.1.2.3 Bits <7:0> DATA (Received Data, Read Only)
      • 6.1.3 Transmit Control and Status Registers (Read/Write)
        • 6.1.3.1 Bit <13> LP (Loopback, Write Only)
        • 6.1.3.2 Bit <12> BRK (Break, Write Only)
        • 6.1.3.3 Bits <11:9> Baud Rate (Write Only)
        • 6.1.3.4 Bit <8> BRE (Baud Rate Enable, Write Only)
        • 6.1.3.5 Bit <7> RDY (Ready, Read Only)
        • 6.1.3.6 Bit <6> IE (Interrupt Enable, Read/Write)
      • 6.1.4 Transmit Data Buffer Registers (Write Only)
        • 6.1.4.1 Bits <11:8> of TXDB (ID Field, Write Only)
        • 6.1.4.2 Bits <7:0> of TXDB (Command or Transmit Data, Write Only)
        • 6.1.4.3 Bits <7:0> of TXDB1, 2, and 3 (Transmit Data, Write Only)
    • 6.2 Using the EEPROM
    • 6.3 Boot RAM
    • 6.4 Using the Watch Chip
      • 6.4.1 Watch Chip CSR A, Address 200B 8014
      • 6.4.2 Watch Chip CSR B, Address 200B 8016
      • 6.4.3 Watch Chip CSR C, Address 200B 8018
      • 6.4.4 Watch Chip CSR D, Address 200B 801A
      • 6.4.5 Bootstrap Software Date and Time Responsibilities
      • 6.4.6 Compatibility with VMS and ULTRIX
    • 6.5 Controlling the RCX50 Controller
      • 6.5.1 Data Transfer Examples
      • 6.5.2 Register RX5CS0, Address 200B 0004
        • 6.5.2.1 RX5CS0 Command Function
        • 6.5.2.2 RX5CS0 Data Transfer Status and Maintenance Status
      • 6.5.3 Register RX5CS1, Address 200B 0006
        • 6.5.3.1 RX5CS1 Command Function, Track Register
        • 6.5.3.2 RX5CS1 Data Transfer and Maintenance Status Format, Error Register
      • 6.5.4 Register RX5CS2, Address 200B 0008
        • 6.5.4.1 RX5CS2 Data Transfer Format, Sector Register
        • 6.5.4.2 RX5CS2 Data Transfer and Maintenance Status Format, Current Track Register
      • 6.5.5 Register RX5CS3, Address 200B 000A
        • 6.5.5.1 RX5CS3 Data Transfer Status Format, Current Sector Register
        • 6.5.5.2 RX5CS3 Maintenance Status Format, Current Status Register
      • 6.5.6 Register RX5CS4, Address 200B 000C
        • 6.5.6.1 RX5CS4 Data Transfer Status, Incorrect Track Register
        • 6.5.6.2 RX5CS4 Maintenance Status, System Configuration Register
      • 6.5.7 Register RX5CS5, Address 200B 000E
      • 6.5.8 Register RX5EB, Empty Sector Buffer Register, Address 200B 0010
      • 6.5.9 Register RX5CA, Clear Address Register, Address 200B 0012
      • 6.5.10 Register RX5GO, Start Command Register, Address 200B 0014
      • 6.5.11 Register RX5FB, Fill Sector Buffer Register, Address 200B 0016
  • Chapter 7 KA820 Diagnostics
    • 7.1 Load Paths
    • 7.2 Test Sequence and Repair Recommendations
    • 7.3 EVKAA, Hard-Core Instruction Test
      • 7.3.1 Booting EVKAA on the Primary Processor
      • 7.3.2 EVKAA Prerequisites and Functions
    • 7.4 Using VDS Stand-Alone
      • 7.4.1 Booting VDS Stand-Alone on the Primary Processor
      • 7.4.2 Booting VDS Stand-Alone on an Attached Processor
      • 7.4.3 Help
      • 7.4.4 Attaching and Selecting the KA820 Module
      • 7.4.5 Flags in VDS
      • 7.4.6 Test Repetitions
    • 7.5 Using VDS On-Line
    • 7.6 EVKAB, VAX Basic Instruction Exerciser
    • 7.7 EVKAC, Floating-Point Instruction Exerciser
    • 7.8 EVKAE, VAX Privileged Architecture Exerciser
    • 7.9 EVKEX, VAX 8200-Specific Cluster Exerciser
    • 7.10 EBDAN, KA820 Serial-Line Unit Diagnostic
  • Appendix A KA820 Module I/O Pins and Cables
    • A.1 Module I/O Pin Definitions
    • A.2 Cables Related to the KA820
  • Appendix B Module Installation and Access to Cables
    • B.1 Module Installation and Replacement
    • B.2 Gaining Access to the Cables
  • Appendix C Drive Load Characteristics of Off-Board Signals
    • C.1 Serial-Line Unit Signals
    • C.2 PCI Bus Off-Board Signals
  • Appendix D BIIC Registers
    • D.1 Device Register, DTYPE (R/W, DMW, DCLOL)
    • D.2 VAXBI Control and Status Register, VAXBICSR
    • D.3 Bus Error Register, BER (W1C, DCLOC)
      • D.3.1 Bus Error Register Hard Error Bits
      • D.3.2 Bus Error Register Parity Mode
      • D.3.3 Bus Error Register Soft Error Bits
    • D.4 Error Interrupt Control Register, EINTRCSR
    • D.5 BCI Control and Status Register, BCICSR
    • D.6 Receive Console Data Register, RXCD
      • D.6.1 MFPR Instruction for the RXCD Register
      • D.6.2 MTPR Instruction for the RXCD Register
  • Appendix E Port Controller Control and Status Register
  • Appendix F Internal Processor Registers on the KA820 Module
  • Appendix G Register Contents at Power-Up and Boot Entry
  • Appendix H EEPROM Contents
  • Appendix I Software Boot Control Flags
  • Appendix J Sample Bootstrap Code
    • J.1 EEPROM Bootstrap Dispatcher
    • J.2 Sample RX50 Bootstrap Code
    • J.3 Sample DU Series Bootstrap Code (MSCP Devices)
  • Appendix K Unexpected Error Conditions
    • K.1 ID Parity Error Interrupts Following Retry Timeout
    • K.2 Clearing the Bus Error Register
    • K.3 Interrupts Following Initialization

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