VCB02 Video Subsystem Technical Manual

Company:Digital Equipment Corporation
Part:EK-104AA-TM-001
Date:1987-02
Keywords:LK201
Supersedes:

Table of Contents

  • Chapter 1 General Description
    • 1.1 Introduction
    • 1.2 Base Module
    • 1.3 Four-Plane Module
    • 1.4 Principal Features of the VCB02 Video Subsystem
    • 1.5 Operational Description
      • 1.5.1 Multiplane Support
      • 1.5.2 Viewport Support
      • 1.5.3 Rasterops
        • 1.5.3.1 Programmable Modes
        • 1.5.3.2 Video Processor Data Manipulation
        • 1.5.3.3 Performance
      • 1.5.4 Private Memory
      • 1.5.5 MicroVAX CPU-to-Address/Video Processor Chip Interface
        • 1.5.5.1 Address Processor Chip Registers
        • 1.5.5.2 Video Processor Chip Registers
    • 1.6 Applications
      • 1.6.1 Text
        • 1.6.1.1 Font Storage and Access
        • 1.6.1.2 Normal Text
        • 1.6.1.3 Character Attributes
      • 1.6.2 Graphics
        • 1.6.2.1 Vectors
        • 1.6.2.2 Fill Mode -- Polygons
        • 1.6.2.3 Polygon Flood
        • 1.6.2.4 Objects
  • Chapter 2 Configurations and Installation
    • 2.1 General
    • 2.2 System Configuration
      • 2.2.1 System Components
        • 2.2.1.1 BA23 Enclosure
        • 2.2.1.2 BA123 Enclosure
        • 2.2.1.3 KA630-AA CPU Module
        • 2.2.1.4 MS630 Memory Expansion Module
        • 2.2.1.5 VCB02 Video Subsystem
        • 2.2.1.6 Mass Storage
        • 2.2.1.7 Ethernet Controller (DEQNA) Module
        • 2.2.1.8 Monitors
        • 2.2.1.9 Monitor Cables
        • 2.2.1.10 LK201 Keyboard
        • 2.2.1.11 Mouse
      • 2.2.2 Options
        • 2.2.2.1 Additional Memory
        • 2.2.2.2 Optional Tape Storage
        • 2.2.2.3 Digitizing Tablet
        • 2.2.2.4 Printers
        • 2.2.2.5 Communication Devices
    • 2.3 System Specifications
      • 2.3.1 BA23 Enclosure -- Electrical
      • 2.3.2 BA123 Enclosure -- Electrical
      • 2.3.3 Environmental
      • 2.3.4 VCB02 Power Requirements
    • 2.4 VCB02 Video Subsystem Installation
      • 2.4.1 Intermodule Connections
        • 2.4.1.1 Common Intermodule Connections
        • 2.4.1.2 Unique Intermodule Connections
      • 2.4.2 I/O Connections
        • 2.4.2.1 Mechanical Connections
  • Chapter 3 Functional Description
    • 3.1 Subsystem Overview
    • 3.2 VCB02 Modules
      • 3.2.1 Base Module
        • 3.2.1.1 Instruction/Data Interconnect
        • 3.2.1.2 Subsystem Timing Generation
        • 3.2.1.3 Video Output Logic
        • 3.2.1.4 I/O Devices
        • 3.2.1.5 System Support
        • 3.2.1.6 Control and Status Registers (CSRs)
        • 3.2.1.7 Console Emulation
        • 3.2.1.8 Diagnostic Support
      • 3.2.2 Four-Plane Module
        • 3.2.2.1 Video Memory Structure
    • 3.3 Address and Video Processor Overview
      • 3.3.1 Hardware Support
        • 3.3.1.1 Buses
        • 3.3.1.2 Bitmap Memory
        • 3.3.1.3 Timing
      • 3.3.2 Memory Organization
      • 3.3.3 Subsystem Control
      • 3.3.4 Viewport Support
        • 3.3.4.1 Scrolling
        • 3.3.4.2 Dragging
        • 3.3.4.3 Clearing a Region
        • 3.3.4.4 Drawing in the Scrolling Region
      • 3.3.5 Multiplane Support
        • 3.3.5.1 Z-Axis Addressing
      • 3.3.6 Basic Address Calculation and Data Path Hardware
        • 3.3.6.1 Address Processor Chip -- Addressing
        • 3.3.6.2 Video Processor Chip -- Data Manipulation
        • 3.3.6.3 Processor-to-Bitmap and Bitmap-to-Processor Transfers
        • 3.3.6.4 Performance
      • 3.3.7 Application to Text
        • 3.3.7.1 Font Storage and Access
        • 3.3.7.2 Normal Text
        • 3.3.7.3 Variable-Pitch Text
        • 3.3.7.4 Rotated and Scaled Text
        • 3.3.7.5 Character Attributes
      • 3.3.8 Application to Graphics and Additional Graphics Support
        • 3.3.8.1 Points and Vectors
        • 3.3.8.2 Shading of Vectors -- Linear and Tile Patterns
        • 3.3.8.3 Fill Mode -- Polygons
        • 3.3.8.4 Polygon Flood
        • 3.3.8.5 Objects
    • 3.4 Address Processor and Video Processor Chip Registers and Commands
      • 3.4.1 Address Processor Chip Registers and Commands
        • 3.4.1.1 Address Processor Chip Registers
        • 3.4.1.2 Address Processor Chip Commands
      • 3.4.2 Video Processor Chip (I/D Bus) Commands
        • 3.4.2.1 Video Processor Chip Registers
        • 3.4.2.2 Instruction/Data Bus Instructions
      • 3.4.3 Physical Configurations
        • 3.4.3.1 Address Processor Chip Pins
        • 3.4.3.2 Video Processor Chip Pins
        • 3.4.3.3 Initialization
    • 3.5 DMA Gate Array
      • 3.5.1 Address Decoding
        • 3.5.1.1 ROMENB Decode
        • 3.5.1.2 RAMOE Decode
        • 3.5.1.3 Address Processor Chip Addresses
        • 3.5.1.4 Gate Array Addresses
        • 3.5.1.5 IOENB Decode
      • 3.5.2 DMA Engine
        • 3.5.2.1 Processor-to-Bitmap Transfers
        • 3.5.2.2 Bitmap-to-Processor Transfers
        • 3.5.2.3 Display List Transfers
      • 3.5.3 Interrupt Controller
      • 3.5.4 Cursor Logic
      • 3.5.5 Display List Data and Commands
        • 3.5.5.1 Display List Data
        • 3.5.5.2 JMPT @ ADDRESS Command
        • 3.5.5.3 PTB NWORDS Command
        • 3.5.5.4 Other Display List Commands
      • 3.5.6 Register Descriptions
        • 3.5.6.1 Control and Status Register (Register 0)
        • 3.5.6.2 DMA Address Counter (15:00) (Register 1)
        • 3.5.6.3 DMA Address Counter (21:16) (Register 2)
        • 3.5.6.4 DMA Byte Counter (15:00) (Register 3)
        • 3.5.6.5 DMA Byte Counter (21:16) (Register 4)
        • 3.5.6.6 FIFO Register (Register 5)
        • 3.5.6.7 Cursor X Position Register (Register 6)
        • 3.5.6.8 Cursor Y Position Register (Register 7)
        • 3.5.6.9 Interrupt Register (Register 8)
        • 3.5.6.10 Memory Base Address Register
      • 3.5.7 Signal Description
        • 3.5.7.1 Q22-Bus Interface
        • 3.5.7.2 Address Decodes
        • 3.5.7.3 Interrupt Inputs
        • 3.5.7.4 Address Processor Chip Interface
        • 3.5.7.5 Template RAM Interface
        • 3.5.7.6 Private Data Bus
        • 3.5.7.7 Cursor Signals
        • 3.5.7.8 Miscellaneous Signals
      • 3.5.8 Physical Description
        • 3.5.8.1 Package Pin Numbering
        • 3.5.8.2 Pin Signal Assignments
      • 3.5.9 Input/Output Specifications
      • 3.5.10 Timing Diagrams
        • 3.5.10.1 Private Bus Timing
        • 3.5.10.2 Q22-Bus Timing
  • Chapter 4 Programming Information
    • 4.1 Programming the VCB02 Video Subsystem
      • 4.1.1 Hardware Support
      • 4.1.2 Bitmap Memory Organization
      • 4.1.3 Overview of Rasterops
      • 4.1.4 Overview of Scrolling
      • 4.1.5 Coordinate Systems and Mapping
        • 4.1.5.1 Interactions between Rasterops and Scrolling
      • 4.1.6 Additional Operations on Bitmap Data
    • 4.2 Video Processor and Address Processor Chip Architecture
      • 4.2.1 Address Processor Chip Architecture
      • 4.2.2 Address Processor Chip Interface to the Q22-Bus
      • 4.2.3 Video Processor Chip Architecture
        • 4.2.3.1 Data Flow for Scrolling and Screen Refresh
        • 4.2.3.2 Rasterop Data Flow
      • 4.2.4 I/D Interconnect Protocol
      • 4.2.5 Rasterop Process
        • 4.2.5.1 Raster Scanning Algorithm
        • 4.2.5.2 Specification of Operands for a Rasterop
        • 4.2.5.3 Model of Raster Operation
      • 4.2.6 Polygon Fill
        • 4.2.6.1 Polygon Fill Model
        • 4.2.6.2 Side Effects of the Fill Algorithm
      • 4.2.7 Processor/Bitmap Transfers
        • 4.2.7.1 Single-Plane Bitmap-to-Processor Transfers
        • 4.2.7.2 Single-Plane Processor-to-Bitmap Transfers
        • 4.2.7.3 Z-Axis Processor/Bitmap Transfers
    • 4.3 Address Processor Chip Description
      • 4.3.1 Coordinate Systems
      • 4.3.2 Address Processor Chip Commands
        • 4.3.2.1 Rasterop Command
        • 4.3.2.2 Processor/Bitmap Transfers
    • 4.4 Video Processor Chip Description
      • 4.4.1 Z-Axis Addressing Mode
      • 4.4.2 Z-Axis Register Loads
  • Chapter 5 Diagnostics
    • 5.1 Overview
    • 5.2 Operation
    • 5.3 Implementation
      • 5.3.1 Performance
      • 5.3.2 Compatibility
      • 5.3.3 Hardware Failure
      • 5.3.4 Unexpected Traps
      • 5.3.5 Power Failures
      • 5.3.6 Restrictions
    • 5.4 Diagnostic Operational Requirements
      • 5.4.1 Hardware
      • 5.4.2 Software
    • 5.5 Functional Description
      • 5.5.1 Power-Up Self-Test
        • 5.5.1.1 Parameters Passed and Returned
        • 5.5.1.2 VCB02 Diagnostic LEDs
        • 5.5.1.3 Register Access and Data Test
        • 5.5.1.4 Template RAM Test
        • 5.5.1.5 Address Processor Test
        • 5.5.1.6 Address Processor and Video Processor Initialization Test
        • 5.5.1.7 Update Video Processor Enable Chip Select Test
        • 5.5.1.8 Bitmap Memory Test
        • 5.5.1.9 Right Scroll Test
        • 5.5.1.10 Down Scroll Test
        • 5.5.1.11 DMA Test
        • 5.5.1.12 Video Synchronization Pulse Test
        • 5.5.1.13 Video Signal Level Test
        • 5.5.1.14 DUART Test
        • 5.5.1.15 Manual Input Devices Test
        • 5.5.1.16 Calling Sequence
      • 5.5.2 Console I/O
        • 5.5.2.1 Put Character Poll
        • 5.5.2.2 Put Character
        • 5.5.2.3 Get Character
        • 5.5.2.4 Enable VCB02 ROM and Console Bus Reset
        • 5.5.2.5 Enable VCB02 ROM and Console Reset
        • 5.5.2.6 N Reset
        • 5.5.2.7 Keyboard Put Character
        • 5.5.2.8 Software Service
        • 5.5.2.9 VCB02 I/O Space CSR Address
        • 5.5.2.10 U.S. Font Table
        • 5.5.2.11 Multinational Font Table
        • 5.5.2.12 Keycode Translate Character
        • 5.5.2.13 Row and Column Parameters
        • 5.5.2.14 VCB02 Memory Space CSR Base
        • 5.5.2.15 Wait 1 Millisecond
  • Appendix A Q22-Bus Specification
    • A.1 General Description
      • A.1.1 Master/Slave Relationship
    • A.2 Q22-Bus Signal Assignments
    • A.3 Data Transfer Bus Cycles
      • A.3.1 Bus Cycle Protocol
      • A.3.2 Device Addressing
    • A.4 Direct Memory Access
      • A.4.1 DMA Protocol
      • A.4.2 Block Mode DMA
        • A.4.2.1 DATBI
        • A.4.2.2 DATBO
      • A.4.3 DMA Guidelines
    • A.5 Interrupts
      • A.5.1 Device Priority
      • A.5.2 Interrupt Protocol
      • A.5.3 Q22-Bus 4-Level Interrupt Configurations
    • A.6 Control Functions
      • A.6.1 Memory Refresh
      • A.6.2 Halt
      • A.6.3 Initialization
      • A.6.4 Power Status
      • A.6.5 BDCOK H
      • A.6.6 BPOK H
      • A.6.7 Power-Up/Down Protocol
    • A.7 Q22-Bus Electrical Characteristics
      • A.7.1 Load Definition
      • A.7.2 120-Ohm Q22-Bus
      • A.7.3 Bus Drivers
      • A.7.4 Bus Receivers
      • A.7.5 Bus Termination
      • A.7.6 Bus Interconnecting Wiring
        • A.7.6.1 Backplane Wiring
        • A.7.6.2 Intra-Backplane Bus Wiring
        • A.7.6.3 Power and Ground
    • A.8 System Configurations
      • A.8.1 Power Supply Loading
    • A.9 Module Contact Finger Identification
  • Appendix B LK201 Keyboard Specification
    • B.1 General Description
    • B.2 Physical Description
    • B.3 Block Diagram Description
      • B.3.1 Keyboard Scanning
      • B.3.2 Control of Audio Transducer and Indicators
      • B.3.3 Keyboard Firmware Functions
        • B.3.3.1 Functions Not Changed by the System's Central Processor Instructions
        • B.3.3.2 Functions Changed by the System's Central Processor Instructions
        • B.3.3.3 Firmware Functions That Can Be Changed
    • B.4 Detailed Keyboard Circuit Description
      • B.4.1 Keyboard Matrix Scanning
      • B.4.2 Audio Transducer Control Circuit
      • B.4.3 Indicator (LED) Control Circuit
      • B.4.4 Keyboard Communication
        • B.4.4.1 Keyboard Transmit Mode
        • B.4.4.2 Keyboard Receive Mode
      • B.4.5 Reset Signal for the 8051 Microprocessor
      • B.4.6 Hardware Keyboard Identification (ID)
      • B.4.7 Voltage Supplies
    • B.5 Keyboard Programming
      • B.5.1 Keyboard Layout and Key Identification
      • B.5.2 Modes
        • B.5.2.1 Special Considerations Regarding Auto-Repeat
        • B.5.2.2 Special Considerations Regarding Down/Up Mode
        • B.5.2.3 Auto-Repeat Rates
      • B.5.3 Keyboard Peripherals
        • B.5.3.1 Audio
        • B.5.3.2 Indicators (LEDs)
      • B.5.4 Keyboard-to-System Module Protocol
        • B.5.4.1 Keycode Transmission
        • B.5.4.2 Special Code Transmission
        • B.5.4.3 Power-Up Transmission
      • B.5.5 System Module-to-Keyboard Protcol
        • B.5.5.1 Commands
        • B.5.5.2 Parameters
        • B.5.5.3 Peripheral Commands
        • B.5.5.4 Mode Set Commands
      • B.5.6 Special Considerations
        • B.5.6.1 Error Handling
        • B.5.6.2 Keyboard Locked Condition
        • B.5.6.3 Reserved Code
        • B.5.6.4 Test Mode
        • B.5.6.5 Future Expansion
      • B.5.7 Default Conditions
    • B.6 Specifications
    • B.7 Character Sets
    • B.8 Character Set Selection
    • B.9 Displaying Characters
  • Appendix C Mouse Specifications
    • C.1 General Description
    • C.2 Installation
      • C.2.1 System Hook-up
      • C.2.2 Installing/Removing the Mouse Ball
    • C.3 Using the Mouse
    • C.4 Mouse Specifications
      • C.4.1 Signal/Power Cable
      • C.4.2 Spurious Outputs
    • C.5 Electrical Interface
      • C.5.1 Interface Signal Levels
      • C.5.2 Power and Voltage Considerations
    • C.6 Mouse Operation
      • C.6.1 Serial Interface Operation
      • C.6.2 Report Format
      • C.6.3 Operating Modes
      • C.6.4 Summary of Mouse Commands
      • C.6.5 Power-Up Self-Test and Identification
      • C.6.6 Report Synchronization
      • C.6.7 Response Time
    • C.7 Programming Considerations
      • C.7.1 Initialization
      • C.7.2 Incremental Stream Mode vs. Prompt Mode
      • C.7.3 Button Use
      • C.7.4 Tablet Support
  • Appendix D Digitizing Tablet Specification
    • D.1 General Description
    • D.2 Electrical Specifications (Power Rating)
    • D.3 Communication Specifications
      • D.3.1 Serial Interface
      • D.3.2 Electrical Signals
      • D.3.3 Tablet Position Report
    • D.4 Tablet Operation and Commands
      • D.4.1 Report Rate
      • D.4.2 Baud Rate Command
      • D.4.3 Request Point Mode
      • D.4.4 Incremental Stream Mode
      • D.4.5 Self-Test
      • D.4.6 Default Conditions
      • D.4.7 Report Synchronization
      • D.4.8 Recovery from Invalid Commands
      • D.4.9 Summary of Digitizing Tablet Commands
    • D.5 Performance Specifications
      • D.5.1 Resolution
      • D.5.2 Accuracy
      • D.5.3 Spurious Outputs
      • D.5.4 Response Time
      • D.5.5 Initialization
    • D.6 Environmental Specifications

Copies

Address: http://vt100.net/dec/ek-104aa-tm-001.pdf
Site: Paul Williams' VT100.net
Format: PDF
Size: 26992445 bytes (25.7 MiB)
MD5: abab7f5979b10ec1c502c9614a0a4b46
Mirrors:
 
Address: http://manx-docs.org/collections/hcps/104aatm1.pdf
Site: hcps collection
Format: PDF
Size: 124488168 bytes (118.7 MiB)
MD5: 06a2bdc891028447c4bb1b0cd9f617bf
Amended to: