PDP-11/24 System Technical Manual

Company:Digital Equipment Corporation
Part:EK-11024-TM-PRE
Date:1981
Keywords:KDF11-UA
Superseded by:

Table of Contents

  • Chapter 1 Introduction
    • 1.1 Manual Scope
    • 1.2 System Overview
    • 1.3 PDP-11/24 Central Processor
      • 1.3.1 CPU Data and Control Chips
      • 1.3.2 Memory Management
      • 1.3.3 Operator's Console
      • 1.3.4 Serial Line Units
      • 1.3.5 Line Time Clock
      • 1.3.6 Bootstrap
      • 1.3.7 UNIBUS Termination
      • 1.3.8 MS11-L MOS Memory System
      • 1.3.9 Floating-Point Processor
      • 1.3.10 Commercial Instruction Set Processor
    • 1.4 General-Purpose Registers
    • 1.5 Addressing Memory and Peripherals
    • 1.6 Addressing Modes
    • 1.7 Instruction Set
    • 1.8 Configuration
      • 1.8.1 BA11-L Mounting Box
      • 1.8.2 BA11-A Mounting Box
      • 1.8.3 System Configuration
    • 1.9 PDP-11/24 Backplane
    • 1.10 Specifications
  • Chapter 2 Installation
    • 2.1 General
    • 2.2 Site Considerations
      • 2.2.1 Humidity and Temperature
      • 2.2.2 Air-Conditioning
      • 2.2.3 Acoustical Damping
      • 2.2.4 Lighting
      • 2.2.5 Special Mounting Conditions
      • 2.2.6 Static Electricity
    • 2.3 Electrical Requirements
      • 2.3.1 System Grounding
    • 2.4 Unpacking
      • 2.4.1 PDP-11/24-AA, AC, BC Unit Removal
      • 2.4.2 PDP-11/24 System Cabinet Removal
    • 2.5 Initial Inspection
    • 2.6 Installation
      • 2.6.1 BA11-L Installation
      • 2.6.2 BA11-A Installation
        • 2.6.2.1 Index Plate Mounting
        • 2.6.2.2 Slide Assembly Mounting
        • 2.6.2.3 Mounting Box to Slide Installation
      • 2.6.3 PDP-11/24 System Cabinet Installation
        • 2.6.3.1 Expander Cabinet Installation
        • 2.6.3.2 Stabilizer Installation
    • 2.7 Module Utilization in a Typical System
    • 2.8 Module Jumper and Switch Configuration
      • 2.8.1 CPU Module (M7133)
      • 2.8.2 M9312 Bootstrap/Terminator Module
        • 2.8.2.1 M9312 Jumper Configuration
        • 2.8.2.2 M9312 ROMs
      • 2.8.3 UNIBUS Map Module (M7134)
        • 2.8.3.1 UNIBUS Map Module Jumper Leads and Memory Page Selection
        • 2.8.3.2 Diagnostic and Bootstrap Loader ROMs
        • 2.8.3.3 Voltage Monitor Switch Selection
    • 2.9 Initial Power-Up and System Checkout
      • 2.9.1 Power Check
      • 2.9.2 Power-Up
  • Chapter 3 PDP-11/24 Operation
    • 3.1 Console Operation
      • 3.1.1 Operator's Console Switches
      • 3.1.2 Operator's Console Indicators
    • 3.2 Console Terminal
      • 3.2.1 ODT Operation
      • 3.2.2 ODT Entry Conditions
    • 3.3 ODT Command Set
      • 3.3.1 Address Specification
      • 3.3.2 Processor I/O Addresses
      • 3.3.3 Entering of Octal Digits
      • 3.3.4 ODT Timeout
      • 3.3.5 Memory Parity Errors
      • 3.3.6 Invalid Characters
      • 3.3.7 Correcting Type-In Errors
    • 3.4 PDP-11/24 Registers
      • 3.4.1 Processor Status Word
      • 3.4.2 Serial Line Unit 1 Registers
        • 3.4.2.1 SLU1 Receiver Control/Status Register (RCSR)
        • 3.4.2.2 SLU1 Receiver Data Buffer (RBUF)
        • 3.4.2.3 SLU1 Transmitter Control/Status Register (XCSR)
        • 3.4.2.4 SLU1 Transmitter Buffer Register (XBUF)
      • 3.4.3 Serial Line Unit 2 Registers
        • 3.4.3.1 SLU2 Receiver Control/Status Register (RCSR)
        • 3.4.3.2 SLU2 Receiver Data Buffer (RBUF)
        • 3.4.3.3 SLU2 Transmitter Control/Status Register (XCSR)
        • 3.4.3.4 TU58 Transmitter Buffer Register (XBUF)
      • 3.4.4 Line Time Clock Control/Status Register (LTC)
      • 3.4.5 Memory Management Registers
        • 3.4.5.1 Status Register 0 (SR0)
        • 3.4.5.2 Status Register 1 (SR1)
        • 3.4.5.3 Status Register 2 (SR2)
        • 3.4.5.4 Status Register 3 (SR3)
      • 3.4.6 Display Register
  • Chapter 4 CPU Functional Description
    • 4.1 Introduction
      • 4.1.1 Central Processor
      • 4.1.2 Processor Options
        • 4.1.2.1 Memory Management Unit
        • 4.1.2.2 Floating Point
        • 4.1.2.3 Commercial Instruction Set
    • 4.2 Timing
      • 4.2.1 Timing Cycles
        • 4.2.1.1 Short Cycle
        • 4.2.1.2 Input/Output Cycles
      • 4.2.2 Timing Logic
    • 4.3 PDP-11/24 Central Processor
      • 4.3.1 Control Path
      • 4.3.2 Microinstruction Bus (MIB <15:00>)
      • 4.3.3 PDP-11/24 Data Path
      • 4.3.4 Data Address Lines (DAL<15:00>)
    • 4.4 PDP-11/24 Chip Set Control Logic
    • 4.5 System Bus Logic
      • 4.5.1 Address and Data
        • 4.5.1.1 Address
        • 4.5.1.2 Data Paths
        • 4.5.1.3 Direct Memory Access
      • 4.5.2 System Bus Timing
      • 4.5.3 System Bus Errors
        • 4.5.3.1 Timeout Error
        • 4.5.3.2 Parity Error
    • 4.6 Internal Address Decode
    • 4.7 Serial Line Inputs
      • 4.7.1 Console Terminal SLU
        • 4.7.1.1 Transmitter Operation
        • 4.7.1.2 Receiver Operation
        • 4.7.1.3 SLU1 Maintenance Configuration
      • 4.7.2 Serial Line Unit 2
        • 4.7.2.1 Transmitter Operation (SLU2)
        • 4.7.2.2 SLU2 Receiver Operation
      • 4.7.3 Baud Rate Logic
    • 4.8 Line Time Clock (LTC)
    • 4.9 Display Register
    • 4.10 Interrupt Request Logic
    • 4.11 Interrupt Errors
      • 4.11.1 SACK Timeout
      • 4.11.2 Vector Timeout
  • Chapter 5 Memory Management
    • 5.1 Introduction
    • 5.2 Relocation
      • 5.2.1 Address Mapping
      • 5.2.2 Address Translation
        • 5.2.2.1 18-Bit Mapping
        • 5.2.2.2 22-Bit Mapping
        • 5.2.2.3 Physical Addressing
    • 5.3 Memory Management Registers
      • 5.3.1 Page Address Register (PAR)
      • 5.3.2 Page Description Registers (PDR)
    • 5.4 Memory Management Status Registers
      • 5.4.1 Status Register 0 (SR0)
      • 5.4.2 Status Register 1 (SR1)
      • 5.4.3 Status Register 2 (SR2)
      • 5.4.4 Status Register 3 (SR3)
    • 5.5 Microinstruction Register (MIR)
    • 5.6 Memory Management Enable (MME) Logic
    • 5.7 Memory Management Timing
    • 5.8 Memory Management Control Signals
  • Chapter 6 KT24 UNIBUS Map Option
    • 6.1 Introduction
    • 6.2 UNIBUS Map
      • 6.2.1 MSYN Steering
      • 6.2.2 Map Control
      • 6.2.3 Map Addressing and Relocation
      • 6.2.4 Addressing Limits
    • 6.3 Boot Logic
    • 6.4 Voltage Monitor
    • 6.5 Registers
      • 6.5.1 UNIBUS Map Registers
      • 6.5.2 Last Mapped Address (LMA) Register
      • 6.5.3 CPU Error Register
  • Chapter 7 Floating-Point Processor Functional Description
    • 7.1 Introduction
    • 7.2 Floating-Point Formats
      • 7.2.1 FPP Integer Formats
      • 7.2.2 FPP Precision Formats
      • 7.2.3 Floating-Point Data Word
        • 7.2.3.1 Floating-Point Fraction
        • 7.2.3.2 Floating-Point Exponent
      • 7.2.4 Processing of Floating-Point Exceptions
    • 7.3 Floating-Point Processor Status Register (FPS)
    • 7.4 Floating-Point Instructions
      • 7.4.1 Floating-Point Accumulators
      • 7.4.2 Instruction Formats
    • 7.5 Floating-Point Instructions
      • 7.5.1 Arithmetic Instructions
      • 7.5.2 Floating-Modulo Instruction
      • 7.5.3 Load Instruction
      • 7.5.4 Store Instruction
      • 7.5.5 Load Convert (Double-to-Floating, Floating-to-Double Instructions)
      • 7.5.6 Store Convert (Double-to-Floating, Floating-to-Double Instructions)
      • 7.5.7 Clear Instruction
      • 7.5.8 Test Instruction
      • 7.5.9 Absolute Instruction
      • 7.5.10 Negate Instruction
      • 7.5.11 Load Exponent Instruction
      • 7.5.12 Load Convert Integer-to-Floating Instruction
      • 7.5.13 Store Exponent Instruction
      • 7.5.14 Store Convert Floating-to-Integer Instruction
      • 7.5.15 Load FPP's Program Status
      • 7.5.16 Store FPP's Program Status
      • 7.5.17 Store FPP's Status
      • 7.5.18 Copy Floating Condition Codes
      • 7.5.19 Set Floating Mode
      • 7.5.20 Set Double Mode
      • 7.5.21 Set Integer Mode
      • 7.5.22 Set Long-Integer Mode
    • 7.6 Floating-Point Instruction Execution
  • Chapter 8 Commercial Instruction Set Processor
    • 8.1 Introduction
    • 8.2 Character Data Types
    • 8.3 Decimal String Data Types
    • 8.4 CIS Instruction Execution
  • Chapter 9 Maintenance
    • 9.1 Troubleshooting Procedures
    • 9.2 MAINDEC Diagnostic Programs
      • 9.2.1 Diagnostic Designations
      • 9.2.2 Running Diagnostics
        • 9.2.2.1 CJKDB-PDP-11/24 CPU Diagnostic
        • 9.2.2.2 CJKDA-KTF11A Memory Management Diagnostic
        • 9.2.2.3 CJKDF-11/24 Option Diagnostic
        • 9.2.2.4 CZM9B-M9312, 11/24, 11/44 UBI Boot Diagnostic
        • 9.2.2.5 CKKUA-11/24, 11/44 UBI Map Diagnostic
        • 9.2.2.6 CZMSD-MS11 L/M Memory Diagnostic
        • 9.2.2.7 DZKAQ-PDP-11 Power-Fail Diagnostic
        • 9.2.2.8 CJKDC, CJKDD-KEF11-A FP Diagnostic Part 1 and 2
        • 9.2.2.9 CJKDH-KEF11-B CIS Diagnostic
  • Appendix A Comm Regulator
  • Appendix B Floating-Point Instruction Set
  • Appendix C PDP-11/24 Backplane Assignments

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