SBC-11/21 PLUS Single-Board Computer User's Guide

Company:Digital Equipment Corporation
Part:EK-SBC02-UG-001
Date:1984-03
Keywords:falcon

Table of Contents

  • Chapter 1 Introduction
    • 1.1 Introduction
    • 1.2 Specifications
      • 1.2.1 Physical
      • 1.2.2 Power Requirements
      • 1.2.3 Bus Loading
      • 1.2.4 Environmental
    • 1.3 Backplane Pin Identification
    • 1.4 Related Documents
  • Chapter 2 Installation
    • 2.1 Introduction
    • 2.2 Selecting Operational Features
      • 2.2.1 Battery Backup
      • 2.2.2 Wake-Up Circuit
      • 2.2.3 Starting Address
      • 2.2.4 Interrupts
      • 2.2.5 Parallel I/O
      • 2.2.6 Serial I/O
      • 2.2.7 Memories
        • 2.2.7.1 Memory Maps
        • 2.2.7.2 PROMs/EPROMs/EEPROMs
        • 2.2.7.3 RAMs
    • 2.3 Selecting Backplanes and Options
    • 2.4 Power Supply
    • 2.5 External Cables
      • 2.5.1 Parallel I/O Interface (J3)
      • 2.5.2 Serial Line Interfaces (J1 and J2)
    • 2.6 Verifying Operation
      • 2.6.1 Macro-ODT Option
      • 2.6.2 Loopback Connectors
      • 2.6.3 Verification Procedure
  • Chapter 3 Options
    • 3.1 Introduction
    • 3.2 Supported Options
      • 3.2.1 Hardware Options
      • 3.2.2 Software Options
        • 3.2.2.1 RT-11 Operating System
        • 3.2.2.2 MicroPower/Pascal Operating System
    • 3.3 Unsupported Options
  • Chapter 4 Macro-ODT
    • 4.1 Introduction
    • 4.2 Installation and Configuration
    • 4.3 Entry Conditions
      • 4.3.1 Macro-ODT Input Sequence
      • 4.3.2 Macro-ODT Output Sequence
    • 4.4 Macro-ODT Commands
      • 4.4.1 / (ASCII 057) Slash
      • 4.4.2 <CR> (ASCII 15) Carriage Return
      • 4.4.3 <LF> (ASCII 12) Line Feed
      • 4.4.4 R (ASCII 122) Internal Register Designator
      • 4.4.5 S (ASCII 123) Processor Status Word (PSW)
      • 4.4.6 G (ASCII 107) Go
      • 4.4.7 P (ASCII 120) Proceed
      • 4.4.8 DD, DX, DY Bootstraps
      • 4.4.9 X (ASCII 130) Diagnostics
    • 4.5 Initialization
    • 4.6 Warnings and Programming Hints
      • 4.6.1 Error Decoding
      • 4.6.2 ODT Stack Warning
      • 4.6.3 Addresses to Avoid
      • 4.6.4 CPU Priority
      • 4.6.5 Terminal Related Problems
      • 4.6.6 Spurious Halts
      • 4.6.7 Serial I/O Protocol
      • 4.6.8 Interrupt Vector Initialization
      • 4.6.9 Boot ROM Address Scheme
  • Chapter 5 System Architecture
    • 5.1 Introduction
    • 5.2 Microprocessor Architecture
      • 5.2.1 Registers
        • 5.2.1.1 General Registers
        • 5.2.1.2 Status Register
      • 5.2.2 Hardware Stack
      • 5.2.3 Interrupts
    • 5.3 DMA (Direct Memory Access)
    • 5.4 Memory Organization
    • 5.5 Power-Up/Power-Down Facility
  • Chapter 6 Programming Information
    • 6.1 Introduction
    • 6.2 Asynchronous Serial Line Units
      • 6.2.1 Data Baud Rates
      • 6.2.2 Interrupts
    • 6.3 Programming the Parallel I/O Interface
      • 6.3.1 Modes of Operation
        • 6.3.1.1 Port C Register
        • 6.3.1.2 Mode 0 Basic Input/Output
        • 6.3.1.3 Port A and B Registers
        • 6.3.1.4 Port C Register in Mode 0
        • 6.3.1.5 Mode 1 (Strobed Input/Output)
        • 6.3.1.6 Mode 2 (Strobed Bidirectional I/O)
      • 6.3.2 Control Word Register
        • 6.3.2.1 Mode Selection
        • 6.3.2.2 Setting Bits in Port C
      • 6.3.3 Parallel I/O Initialization
      • 6.3.4 Parallel I/O Handshaking
  • Chapter 7 Addressing Modes and Instruction Set
    • 7.1 Introduction
    • 7.2 Addressing Modes
      • 7.2.1 Single Operand Addressing
      • 7.2.2 Double Operand Addressing
      • 7.2.3 Direct Addressing
        • 7.2.3.1 Register Mode (Mode 0)
        • 7.2.3.2 Autoincrement Mode (Mode 2)
        • 7.2.3.3 Autodecrement Mode (Mode 4)
        • 7.2.3.4 Index Mode (Mode 6)
      • 7.2.4 Deferred (Indirect) Addressing
      • 7.2.5 Use of the PC as a General-Purpose Register
        • 7.2.5.1 Immediate Mode
        • 7.2.5.2 Absolute Addressing
        • 7.2.5.3 Relative Addressing
        • 7.2.5.4 Relative Deferred Addressing
      • 7.2.6 Use of the Stack Pointer as a General-Purpose Register
    • 7.3 Instruction Set
      • 7.3.1 Instruction Formats
      • 7.3.2 List of Instructions
      • 7.3.3 Single Operand Instructions
        • 7.3.3.1 General
        • 7.3.3.2 Shifts and Rotates
        • 7.3.3.3 Multiple Precision
        • 7.3.3.4 PS Word Operators
      • 7.3.4 Double Operand Instructions
        • 7.3.4.1 General
        • 7.3.4.2 Logical
      • 7.3.5 Program Control Instructions
        • 7.3.5.1 Branches
        • 7.3.5.2 Signed Conditional Branches
        • 7.3.5.3 Unsigned Conditional Branches
        • 7.3.5.4 Jump and Subroutine Instructions
        • 7.3.5.5 Traps
        • 7.3.5.6 Reserved Instruction Traps
        • 7.3.5.7 HALT Interrupt
        • 7.3.5.8 Trace Trap
        • 7.3.5.9 Power Failure Interrupt
        • 7.3.5.10 Interrupts
        • 7.3.5.11 Special Cases (T-bit)
      • 7.3.6 Miscellaneous Instructions
      • 7.3.7 Condition Code Operators
  • Chapter 8 Theory of Operation
    • 8.1 Introduction
    • 8.2 Microprocessor
      • 8.2.1 Microprocessor Initialization
        • 8.2.1.1 RESET Instruction
        • 8.2.1.2 Power-up Input (PUP)
      • 8.2.2 Clock Input (-TCLK)
      • 8.2.3 Ready Input (READY)
      • 8.2.4 Microprocessor Control Signals
        • 8.2.4.1 Row Address Strobe (RAS)
        • 8.2.4.2 Column Address Strobe (CAS)
        • 8.2.4.3 Priority In (PI)
        • 8.2.4.4 Read/Write (R/-WHB and R/-WLB)
        • 8.2.4.5 Select Output Flags (SEL0 and SEL1)
        • 8.2.4.6 Bus Clear (BCLR)
        • 8.2.4.7 Clock Out (COUT)
      • 8.2.5 Microprocessor Transactions
        • 8.2.5.1 Fetch/Read
        • 8.2.5.2 Write
        • 8.2.5.3 IAK
        • 8.2.5.4 DMA
        • 8.2.5.5 ASPI
        • 8.2.5.6 NOP
    • 8.3 Mode Register Control
    • 8.4 Interrupt Control
      • 8.4.1 Interrupt Control Logic
      • 8.4.2 Ready Logic
      • 8.4.3 IAK Data In (IAKDIN)
      • 8.4.4 HALT Interrupt
      • 8.4.5 Power Fail (-PFAIL)
      • 8.4.6 Local
      • 8.4.7 External
      • 8.4.8 DMA Interrupt
    • 8.5 DC004 Protocol
    • 8.6 Address Latch
    • 8.7 Memory Address Decode
    • 8.8 RAM Memory
    • 8.9 ROM/RAM Memory Sockets
    • 8.10 Serial Line Interface Units
    • 8.11 Parallel I/O Interface
    • 8.12 Power-Up
    • 8.13 Clock
    • 8.14 Clock Control
    • 8.15 DMA
    • 8.16 TSYNC
    • 8.17 Read/Write
    • 8.18 Reply Time-out
    • 8.19 Bus Control
  • Chapter 9 LSI-11 Bus
    • 9.1 Introduction
    • 9.2 SBC-11/21 PLUS Single-Board Computer
    • 9.3 Master/Slave Relationship
    • 9.4 Data Transfer Bus Cycles
      • 9.4.1 Bus Cycle Protocol
      • 9.4.2 Direct Memory Access
    • 9.5 Interrupts
      • 9.5.1 Device Priority
      • 9.5.2 Interrupt Protocol
    • 9.6 Control Functions
      • 9.6.1 Halt
      • 9.6.2 Initialization
      • 9.6.3 Power Status
      • 9.6.4 Power-Up/Power-Down Protocol
    • 9.7 LSI-11 Bus Electrical Characteristics
    • 9.8 Module Contact Finger Identification
  • Appendix A Instruction Timing
  • Appendix B Programming Difference List
  • Appendix C Software Development
    • C.1 General
    • C.2 Running RT-11 V5.1 Operating System
    • C.3 Running MicroPower/Pascal
    • C.4 Running Standalone Programs from TU58 or RX01/02
    • C.5 The Software Development Process
      • C.5.1 Design of the Software
      • C.5.2 Editing and Assembly
      • C.5.3 Building Process
      • C.5.4 Running and Debugging the Program
      • C.6 An Application Example
      • C.6.1 Power-Up Programs
      • C.6.2 Diagnostic Programs
      • C.6.3 Control Task Program
      • C.6.4 Exception Program
  • Appendix D Macro-ODT ROM Listing for KXT11-A2 Option
  • Appendix E Macro-ODT ROM Listing for KXT11-A5 Option
  • Appendix F SBC-11/21 PLUS Schematics
  • Appendix G Glossary
  • Appendix H SBC-11/21 PLUS and SBC-11/21 Differences
    • H.1 Introduction
    • H.2 Overview
    • H.3 Optional FPLA
    • H.4 Memory Maps
    • H.5 KXT11-A2 and KXT11-A5 Macro-ODT ROMs
    • H.6 Memory Devices Supported
    • H.7 Wirewrap Configuration Comparisons
    • H.8 RT-11 on SBC-11/21 PLUS
      • H.8.1 SBC-11/21 PLUS and RT-11(SJ) (SBC-11/21 PLUS mode)
      • H.8.2 SBC-11/21 PLUS with RT-11(FB) (SBC-11/21 PLUS mode)
      • H.8.3 SBC-11/21 PLUS with RT-11(FB) (SBC-11/21 mode)
    • H.9 SBC-11/21 PLUS and MicroPower/Pascal

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