VXT 2000 Windowing Terminal and DECimage 2000 Option Service Information

Company:Digital Equipment Corporation
Part:EK-VXT20-SV.B01
Date:1992-05
Keywords:

Table of Contents

  • 1 A Look at the Terminal
    • 1.1 Product Description
    • 1.2 Terminal Components
      • 1.2.1 Monitor
      • 1.2.2 Keyboard
      • 1.2.3 Mouse
      • 1.2.4 System Box
    • 1.3 Operating Features
      • 1.3.1 X Window Sessions and Terminal Window Sessions
      • 1.3.2 Network Communications Protocols
      • 1.3.3 Terminal Software
      • 1.3.4 Customizing the Terminal
      • 1.3.5 Checking the Terminal's System Configuration
    • 1.4 Site Requirements
      • 1.4.1 Network Hardware Support
      • 1.4.2 Memory Requirements
      • 1.4.3 Hardware Configurations
      • 1.4.4 System Software Support
      • 1.4.5 System Software Support for the DECimage 2000 Module
  • 2 Installing the Terminal
    • 2.1 Installation Steps
      • 2.1.1 Unpack and check the contents of each carton
      • 2.1.2 Install any optional memory, network, or image module first
      • 2.1.3 Place the system box and monitor in position
      • 2.1.4 Connect the cables to the system box
      • 2.1.5 If you installed a DECimage 2000 module
      • 2.1.6 Final steps
  • 3 Testing
    • 3.1 Self-Tests
      • 3.1.1 Running Self-Tests in Console Mode
      • 3.1.2 Checking the Self-Test Results
      • 3.1.3 Diagnostic LED Power-Up Sequence
    • 3.2 Displaying the Software Version Number
    • 3.3 Network Service Failure Messages
    • 3.4 Checking for Memory Errors
      • 3.4.1 Memory Status Messages
      • 3.4.2 Soft Error Messages
    • 3.5 Screen Alignment Patterns
  • 4 Troubleshooting
    • 4.1 Troubleshooting Sequence
    • 4.2 Before You Start
    • 4.3 Hard and Soft Errors
      • 4.3.1 Entering Console Mode After a Hard Error
    • 4.4 Troubleshooting Soft Memory Errors
      • 4.4.1 Troubleshooting Soft Memory Errors by LEDs
    • 4.5 Troubleshooting Hard Errors
    • 4.6 LED Error Codes
    • 4.7 Troubleshooting General Problems
  • 5 Removing and Replacing FRUs
    • 5.1 System Box Cover
    • 5.2 Memory Controller Module
    • 5.3 Memory Modules
      • 5.3.1 Removing Memory Modules
      • 5.3.2 Installing Memory Modules
    • 5.4 Network Module
    • 5.5 DECimage 2000 Module
    • 5.6 Video Module
    • 5.7 System Logic Module
    • 5.8 Power Supply
    • 5.9 Fan
    • 5.10 Keyboard, Mouse, and Printer
  • 6 Starting a Session
    • 6.1 Terminal Manager Window
    • 6.2 Choosing the Display Language
    • 6.3 Choosing the Correct Keyboard Type
    • 6.4 Starting a Session on Your Host System
      • 6.4.1 Creating an IP X Window or TELNET Terminal Window Session
      • 6.4.2 Creating a LAT X Window or Terminal Window Session
      • 6.4.3 Starting a Terminal Window Session on the Serial Port
    • 6.5 Using the Keyboard Instead of the Mouse
    • 6.6 Ending a Session
  • A Related Documents
    • A.1 Ordering Information
  • B Recommended Spares List
  • C Self-Test Error Descriptions
  • Part 1 Unibus Specification
  • Introduction
    • Scope
    • Content
  • Unibus Description
    • Architecture
    • Unibus Transmission Medium
    • Bus Terminator
    • Bus Segment
    • Bus Repeater
    • Bus Master
    • Bus Slave
    • Bus Arbitrator
    • Bus Request
    • Bus Grant
    • Processor
    • Interrupt Fielding Processor
  • Unibus Systems
    • Signal Lines
    • Priority Structure
    • Address Space
    • Latency
    • Arrangement of Devices on the Unibus
    • Expanding the Unibus System
  • Protocol
    • Types of Transactions
    • Priority Arbitration Transactions
    • Data Transfers
    • Initialization
  • Unibus Signal Details
    • Unibus Sections and Signal Lines
    • Signal Transmission
      • Bus Transmission Delay
      • Skew
      • Deskew
    • Types of Unibus Signal Lines
    • Priority Arbitration Section
      • Non-Processor Request (NPR)
      • Non-Processor Grant (NPG)
      • Bus Request (BR4, BR5, BR6, BR7)
      • Bus Grant (BG4, BG5, BG6, BG7)
      • Selection Acknowledged (SACK)
      • Bus Busy (BBSY)
    • Data Transfer Section
      • Data Lines, D<15:00>
      • Address Lines, A<17:00>
      • Control Lines, C0, C1
      • Master Sync (MSYN)
      • Slave Sync (SSYN)
      • Interrupt Request (INTR)
    • Initialization Section
      • Intialize (INIT)
      • AC Low (AC LO)
      • DC Low (DC LO)
  • Unibus Protocols
    • Definitions and Concepts
      • Arbitration
      • Centralized Arbitration
      • Priority Arbitration
      • Data Transfer (Bus Cycle)
      • Transaction
      • Protocol
    • Unibus Operation Concepts
    • Priority Protocol
      • Bus Device Priority Levels
      • Interrupt Fielding Processor CPU Priority Levels
      • Grant
      • Assertion
      • Negation
      • Priority Arbitration Example
      • Priority Arbitration Transactions
      • Notes on the Timing Diagrams
      • NPR Arbitration Sequence
      • BR Interrupt Arbitration Sequence
      • Data Transfer Protocol
        • Data-In Transaction (DATI or DATIP)
        • Detailed Description, DATI and DATIP
        • Data-Out Transaction (DATO or DATOB)
        • Detailed Description, DATO and DATOB
        • Read/Modify/Write Transactions (DATIP-DATO/B)
        • Multiple Word Transfers
  • Initialization Section
    • Initialization (INIT)
      • Processor Requirements
      • Arbitrator Response
      • Master/Slave Response
    • Power-Up and Power-Down Sequences
  • Unibus Interface Design Guidelines
    • Preferred Interface Integrated Circuit (IC) Chips
    • Unibus Transmitter (Driver)
    • Unibus Receiver
    • Bus Receiver and Transmitter Equivalent Circuits
    • DC Bus Load
    • Module Layout
    • Backplanes
    • Grounding
    • Logic Design Guidelines for Unibus Interfaces
    • Master Devices
    • Unibus Control Logic
    • Bus Request (BR) Device---One Vector
    • Bus Request (BR) Device---Two Vectors
    • Non-Processor Request (NPR) Device
  • Unibus Configuration
    • Definitions
      • Unibus Segment
      • Unibus Cable
      • Unibus Element
      • AC Unit Load
      • DC Unit Load
      • Lumped Load
      • Bus Terminator
      • Semi-Lumped Load
      • Data-In Transactions
      • DATIP Transactions
      • Data-Out Transactions
      • Parity Error Indications (PA, PB)
      • Master Sync (MSYN)
      • Slave Sync (SSYN)
      • Interrupt Request (INTR)
      • AC Bus Load
      • DC Bus Load
    • Unibus Configuration Rules
      • Maximum Cable Length (Rule 1)
      • Maximum DC Loading (Rule 2)
      • Maximum AC Loading (Rule 3)
      • Different Cable Lengths (Rule 4)
      • Voltage Margin Tests (Rule 5)
  • Unibus Hardware
    • Unibus Cable (BC11A)
    • M920 Unibus Jumper Module
    • M9202 Unibus Jumper with Cable
    • M930 Unibus Terminator Module
    • M981 Internal Unibus Terminator Assembly
    • Drivers, Receivers, and Transmitters
    • Unibus Connector Block Pin Assignments
  • Part 2 LSI-11 Bus Specification
  • Introduction
    • Master/Slave Relationships
  • Data Transfer Bus Cycles
    • Bus Cycle Protocol
      • Device Addressing
      • DATI
      • DATO(B)
      • DATIO(B)
      • Parity Protocol
    • Direct Memory Access
      • DMA Protocol
  • Interrupts
    • Device Priority
    • Interrupt Protocol
    • 4-Level Interrupt Configurations (LSI-11/23)
  • Control Functions
    • Memory Refresh
    • Halt
    • Initialization
    • Power Status
      • BDCOK H
      • BPOK H
    • Power-Up/Down Protocol
  • Bus Electrical Characteristics
    • AC Load Definition
    • DC Load Definition
    • 120 Ohm LSI-11 Bus
    • Bus Drivers
    • Bus Receivers
    • Bus Termination
    • Bus Interconnecting Wiring
      • Backplane Wiring
      • Intra-Backplane Wiring
      • Power and Ground
  • System Configurations
    • Rules for Configuring Single Backplane Systems
    • Rules for Configuring Multiple Backplane Systems
    • Power Supply Loading
  • Appendix A MASSBUS
  • Appendix B DECdataway
  • Appendix C PCL-11
  • Chapter 1 Introduction
  • Chapter 2 Unibus
  • Chapter 3 Addressing Modes
  • Chapter 4 Instruction Set
  • Chapter 5 Programming Techniques
  • Chapter 6 Memory Management
  • Chapter 7 PDP-11/04, 11/34A
  • Chapter 8 PDP-11/44
  • Chapter 9 PDP-11/60
  • Chapter 10 PDP-11/70
  • Chapter 11 Floating-Point Processors
  • Chapter 12 Commercial Instruction Set
  • Appendix A Unibus Addresses
  • Appendix B Instruction Set
  • Appendix C Conversion Table

Copies

Address: http://computer-refuge.org/classiccmp/dec94mds/vxt20svb.txt
Site: Patrick Finnegan's Computer Refuge
Format: Text
Size: 148741 bytes (145 KiB)
 
Address: http://computer-refuge.org/classiccmp/dec94mds/vxt20svb.pdf
Site: Patrick Finnegan's Computer Refuge
Format: PDF
Size: 1260983 bytes (1.2 MiB)
MD5: c64dcec4ad121c80d9d1ee7e1f26ac7c
 
Address: http://deathrow.vistech.net/~cvisors/DEC94MDS/vxt20svb.txt
Site: Ivy's MDS Mirror (Low Bandwidth)
Format: Text
Size: 148741 bytes (145 KiB)
MD5: 49c619f5bff5f4d0a6f762b39d7dbf73
 
Address: http://deathrow.vistech.net/~cvisors/DEC94MDS/vxt20svb.pdf
Site: Ivy's MDS Mirror (Low Bandwidth)
Format: PDF
Size: 1260983 bytes (1.2 MiB)
MD5: c64dcec4ad121c80d9d1ee7e1f26ac7c
 
Address: http://cmcnabb.cc.vt.edu/dec94mds/vxt20svb.txt
Site: Christopher McNabb's MDS Mirror
Format: Text
Size: 148741 bytes (145 KiB)
MD5: 49c619f5bff5f4d0a6f762b39d7dbf73
 
Address: http://cmcnabb.cc.vt.edu/dec94mds/vxt20svb.pdf
Site: Christopher McNabb's MDS Mirror
Format: PDF
Size: 1260983 bytes (1.2 MiB)
MD5: c64dcec4ad121c80d9d1ee7e1f26ac7c
 
Address: http://www.xenya.si/sup/info/digital/MDS/jun99/Cd3/TERM/VXT20SVB.PDF
Site: www.xenya.si
Format: PDF
Size: 1473349 bytes (1.4 MiB)
MD5: 7ccf2325ca2155f14c296f3b85d4b54c
 
Address: http://manx-docs.org/collections/mds-199909/cd3/term/vxt20svb.pdf
Site: Compaq Maintenance Documentation Service on CD-ROM, DIGITAL-branded Products, September 1999
Format: PDF
Size: 1473349 bytes (1.4 MiB)
MD5: 7ccf2325ca2155f14c296f3b85d4b54c