DECsystem-10/DECSYSTEM-20 Processor Reference Manual

Company:Digital Equipment Corporation
Part:AA-H391A-TK
Date:1982-06
Keywords:

Table of Contents

  • Chapter 1 Introduction
    • 1.1 KL10-based System Organization
      • The KL10 processor
    • 1.2 KS10-based System Organization
    • 1.3 Timesharing
    • 1.4 Number System
      • Floating Point Numbers
      • Expanded Range Floating Point Numbers
    • 1.5 Instruction Format
    • 1.6 Effective Address Calculation
      • Extended Addresses
    • 1.7 KL10 Memory
      • Memory Characteristics
    • 1.8 KS10 Memory
    • 1.9 Programming Conventions
    • 1.10 KI10 and KA10 Characteristics
      • Memory
  • Chapter 2 User Operations
    • 2.1 Full Word Data Transmissions
      • Move Instructions
      • Double Move Instructions
      • Block Transfers
    • 2.2 Fixed Point Arithmetic
      • Single Precision Instructions
      • Double Precision Instructions
    • 2.3 Floating Point Arithmetic
      • Single Precision with Rounding
      • Single Precision without Rounding
      • Standard Range Double Precision
      • Expanded Range Double Precision
      • Number Conversion
      • Scaling
      • KA10 Software Double Precision
    • 2.4 Boolean Functions
    • 2.5 Shift and Rotate
    • 2.6 Arithmetic Testing
    • 2.7 Logical Testing and Modification
    • 2.8 Half Word Data Transmission
    • 2.9 Program Control
      • The Execute Instruction
      • Conditional Jumps
      • Program Flags
      • The JRST Instruction
      • Subroutine Calling
      • Overflow Trapping
    • 2.10 Stack Operations
    • 2.11 Byte Manipulation
    • 2.12 String Manipulation
    • 2.13 Decimal Conversion
    • 2.14 String Editing
    • 2.15 Programming Examples
      • Processor Identification
      • Parity
      • Reversing Order of Digits
      • Counting Ones
      • Number Conversion
      • Table Searching
      • Extended Addressing
    • 2.16 Unimplemented Operations
      • MUUOs
    • 2.17 KS10 Input-Output Instructions
    • 2.18 Pre-KS10 Input-Output Instructions
    • 2.19 User Programming
  • Chapter 3 KL10 System Operations
    • 3.1 Priority Interrupt
      • Interrupt Requests
      • Interrupt Functions and Instructions
      • Interrupt Programming
    • 3.2 Cache Management
      • Cache Programming
    • 3.3 TOPS-10 Paging and Process Tables
      • Paging
      • Page Failure
      • The Map Instruction
    • 3.4 TOPS-20 Paging and Process Tables
      • Paging
      • Page Refill
      • Page Failure
      • The Map Instruction
    • 3.5 Memory Management
      • Previous Context Execute
      • Address Debugging
    • 3.6 Timing and Accounting
      • System Timing
      • User Accounts
      • Performance Analysis
    • 3.7 Front End Functions
    • 3.8 Error and Diagnostic Instructions
      • Error Monitoring and Investigiation
      • S Bus Diagnostic Cycle
  • Chapter 4 KS10 System Operations
    • 4.1 Priority Interrupt
      • Processing an Interrupt
      • Interrupt Processing
    • 4.2 Cache
    • 4.3 TOPS-10 Paging and Process Tables
      • Paging
      • Page Failure
      • The Map Instruction
    • 4.4 TOPS-20 Paging and Process Tables
      • Paging
      • Page Refill
      • Page Failure
      • The Map Instruction
    • 4.5 Memory Management
      • Previous Context Execute
    • 4.6 System Timing
    • 4.7 Halt Status
    • 4.8 System Conditions
      • System Flags
      • Memory Status
  • Chapter 5 KI10 and KA10 System Operations
    • 5.1 Console
      • Readin Mode
      • Console-Program Communication
    • 5.2 KI10 Priority Interrupt
      • Starting an Interrupt
      • Interrupt Programming
    • 5.3 KI10 Processor Conditions
    • 5.4 KI10 Program and Memory Management
      • Paging
      • Page Failure
      • Monitor Programming
      • Previous Context Execute
    • 5.5 KA10 Priority Interrupt
    • 5.6 KA10 Processor Conditions
    • 5.7 KA10 Program and Memory Management
      • Monitor Programming
    • 5.8 Real Time Clock DK10
  • Appendix A Instructions and Mnemonics
  • Appendix B Character Codes
  • Appendix C Internal Device Bit Assignments
  • Appendix D Timing
  • Appendix E Processor Compatibility
  • Appendix F Processor Operation
    • F.1 KI10 Operation
    • F.2 KA10 Operation
  • Appendix G Handling Memory
    • G.1 DECsystem-10 Memories
    • G.2 DECSYSTEM-20 Memories

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