KT11-C Memory Management Unit Maintenance Manual

Company:Digital Equipment Corporation
Part:DEC-11-HKTCA-C-D
Date:1974-01
Keywords:PDP-11

Table of Contents

  • Chapter 1 General Description
    • 1.1 Purpose of Option
    • 1.2 Prerequisite
    • 1.3 Features
      • 1.3.1 Memory Protection
      • 1.3.2 Relocation/Virtual Memory
      • 1.3.3 Memory Expansion
      • 1.3.4 Variable Size Pages
      • 1.3.5 Page State Information
      • 1.3.6 Instruction/Data Spaces
      • 1.3.7 Kernel/Supervisor/User Spaces
      • 1.3.8 Program vs Stack Pages
      • 1.3.9 Fault Recovery
      • 1.3.10 Statistical Traps
    • 1.4 KT11-C Memory Management Unit Specifications
  • Chapter 2 Operation and Programming
    • 2.1 Basic KT11-C Mechanisms
      • 2.1.1 Address Relocation Mechanism
      • 2.1.2 Memory Protection Mechanisms
        • 2.1.2.1 Non-Resident/Read-Only Protection
        • 2.1.2.2 Execute-Only Protection
        • 2.1.2.3 Multiple Address Space Protection
      • 2.1.3 Memory Management Statistics Mechanism
      • 2.1.4 Trap/Abort Mechanism
    • 2.2 PAR/PDR Registers
      • 2.2.1 Page Address Registers (PAR)
      • 2.2.2 Page Description Registers (PDR)
        • 2.2.2.1 Access Control Field (ACF)
        • 2.2.2.2 Expansion Direction (ED)
        • 2.2.2.3 Written Into (W)
        • 2.2.2.4 Attention (A)
        • 2.2.2.5 Page Length Field (PLF)
    • 2.3 Memory Management Status Registers
      • 2.3.1 Status Register 0 (SR0)
        • 2.3.1.1 Abort-Nonresident
        • 2.3.1.2 Abort-Page Length
        • 2.3.1.3 Abort-Read Only
        • 2.3.1.4 Trap-Memory Management
        • 2.3.1.5 Bit 11
        • 2.3.1.6 Enable Memory Management
        • 2.3.1.7 Maintenance/Destination Mode
        • 2.3.1.8 Instruction Completed
        • 2.3.1.9 Abort Recovery Information
        • 2.3.1.10 Enable KT11-C
      • 2.3.2 Status Register 1 (SR1)
      • 2.3.3 Status Register 2 (SR2)
      • 2.3.4 Status Register 3 (SR3)
    • 2.4 KT11-C Operation
      • 2.4.1 Console Operations
        • 2.4.1.1 Single Step Mode
        • 2.4.1.2 Address Display
        • 2.4.1.3 Stepping Over 32K-Word Boundaries
      • 2.4.2 Physical Address Determination
      • 2.4.3 Protection Without Relocation
      • 2.4.4 Communication Between User/Supervisor/Kernel Address Space
        • 2.4.4.1 Overlapping Physical Addresses
        • 2.4.4.2 MFPI and MTPD Instructions Use
        • 2.4.4.3 Control Information
      • 2.4.5 Statistical Aids Use
      • 2.4.6 I and D Space Use
      • 2.4.7 I/O Operations
        • 2.4.7.1 Kernel Mode Protection
        • 2.4.7.2 Avoiding I/O Lockout
      • 2.4.8 Processor Status Word
        • 2.4.8.1 Explicit References to PS
        • 2.4.8.2 Implicit Modification of the PS
      • 2.4.9 Non-Recoverable Aborts
      • 2.4.10 Page Fault Recovery
        • 2.4.10.1 Definitions
        • 2.4.10.2 Program Example
      • 2.4.11 Fatal System Errors
  • Chapter 3 Logic Description
    • 3.1 PDP-11/45 System Interface
    • 3.2 KT11-C Organization
      • 3.2.1 System Address Path (SAP)
      • 3.2.2 Status and Control Logic
    • 3.3 PAR/PDR Registers
      • 3.3.1 Page Address Registers (PAR)
        • 3.3.1.1 Selection
        • 3.3.1.2 Addressing
        • 3.3.1.3 Writing Into a PAR
        • 3.3.1.4 Reading From a PAR
      • 3.3.2 Page Description Registers (PDR)
        • 3.3.2.1 Selection
        • 3.3.2.2 Addressing
        • 3.3.2.3 Writing Into a PDR
        • 3.3.2.4 Setting A or W Bits
        • 3.3.2.5 Clearing A or W Bits
        • 3.3.2.6 Reading From a PDR
    • 3.4 Relocation Logic
      • 3.4.1 Address Inverters/Buffers
      • 3.4.2 12-Bit Adder
      • 3.4.3 Relocation Multiplexer
    • 3.5 Console Address Display and Control
      • 3.5.1 ADDRESS Display
      • 3.5.2 Console Mode Control
    • 3.6 Abort and Trap Decode
      • 3.6.1 Abort Control Logic
        • 3.6.1.1 Non-Resident (NR) Page Fault
        • 3.6.1.2 Resident Read-Only (RRO) Fault
        • 3.6.1.3 Page Length Fault
      • 3.6.2 Internal Register Inhibit
      • 3.6.3 Memory Management Trap Decode
    • 3.7 PAR/PDR Read Multiplexers
    • 3.8 Unibus Address Drivers
    • 3.9 Status Register 3 (SR3)
    • 3.10 KT11-C ROM and Decode
      • 3.10.1 ROM Organization
      • 3.10.2 ROM OUT <4:1> Decoders
        • 3.10.2.1 RESTORE PS
        • 3.10.2.2 SSRA JSR.30 (ROM <3:1> = 5)
        • 3.10.2.3 BRK.30 (ROM <3:1> = 4)
        • 3.10.2.4 AUTO DEC (ROM <3:1> = 3)
        • 3.10.2.5 ONE CHANGED (ROM <3:1> = 2 or 3)
        • 3.10.2.6 DST
      • 3.10.3 Kernel Space Control
      • 3.10.4 Supervisor Space Control
      • 3.10.5 User Space Control
      • 3.10.6 I Space Control
    • 3.11 Status Register 0 (SR0)
      • 3.11.1 Abort Flags SR0 <15:13>
      • 3.11.2 Memory Management Trap (SR0 Bit 12)
        • 3.11.2.1 Enable Management Traps
        • 3.11.2.2 Pre-Management Trap
        • 3.11.2.3 Memory Management Hold
        • 3.11.2.4 Writing Into SR0 Bit 12
      • 3.11.3 Trap Flag (SR0 Bit 11)
      • 3.11.4 DST MODE (SR0 Bit 08)
      • 3.11.5 INSTR COMP (SR0 Bit 07)
      • 3.11.6 SR0 Mode Field (SR0 Bits <06:05>)
      • 3.11.7 Address Space -- I/D (SR0 Bit 04)
      • 3.11.8 Page Number (SR0 Bits <03:01>)
      • 3.11.9 KT11-C Relocating (SR0 Bit 00)
    • 3.12 Status Register 1 (SR1)
      • 3.12.1 General Register Address
      • 3.12.2 Autoincrement/Autodecrement
      • 3.12.3 Examples of SR1 Loading
    • 3.13 Status Register 2 (SR2)
    • 3.14 Internal Data Bus Multiplexers
    • 3.15 KT11-C Memory Managment Timing
      • 3.15.1 Event Times Related to Memory Cycles
      • 3.15.2 Address Relocation Timing
      • 3.15.3 Internal Register Access Timing
    • 3.16 Internal Register Control
      • 3.16.1 PAR/PDR Decode and Control
      • 3.16.2 SSR Decode and Control
        • 3.16.2.1 SSR REG
        • 3.16.2.2 INT SR3
      • 3.16.3 Internal Register Fast Decode
  • Chapter 4 Installation and Maintenance
    • 4.1 Installation
    • 4.2 Maintenance
      • 4.2.1 Diagnostic Programs
      • 4.2.2 Troubleshooting Test Procedures
      • 4.2.3 Repair Procedures
  • Appendix A Glossary
  • Appendix B Reference Literature

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