MK11 MOS Memory Technical Manual

Company:Digital Equipment Corporation
Part:EK-0MK11-TM-001
Date:1978-06
Keywords:PDP-11/70

Table of Contents

  • Chapter 1 Introduction
    • 1.1 Memory System Overview
      • 1.1.1 General Description
      • 1.1.2 Packaging
      • 1.1.3 Memory System Configurations
      • 1.1.4 Options
    • 1.2 Memory System Organization
      • 1.2.1 Main Memory Bus
      • 1.2.2 Address Buffer Module
      • 1.2.3 Data Buffer Module
      • 1.2.4 Control A and B Modules
      • 1.2.5 MOS Memory Array Modules
    • 1.3 Related Hardware Manuals
  • Chapter 2 Main Memory Bus
    • 2.1 General Description
    • 2.2 Protocol and Timing
      • 2.2.1 Initiation of a Memory Cycle
      • 2.2.2 Response of the Memory System
      • 2.2.3 CSR Cycles
      • 2.2.4 Initiation of "Overlapped" Memory Cycles
  • Chapter 3 Box Controller
    • 3.1 General Description
    • 3.2 Control Switches and Indicators
    • 3.3 Starting Address and External Interleaving
    • 3.4 Disabling Error Correction
  • Chapter 4 MS11-KE MOS Array Modules
    • 4.1 General Description
    • 4.2 Functional Description
      • 4.2.1 Data Receivers and Drivers
      • 4.2.2 Addressing and Control
  • Chapter 5 Control Modules
    • 5.1 General Description
      • 5.1.1 Control A Module
      • 5.1.2 Control B Module
    • 5.2 Functional Description
      • 5.2.1 Timing
      • 5.2.2 Address and Control
      • 5.2.3 Data Paths
      • 5.2.4 Error Detection and Correction
    • 5.3 Memory Cycles
      • 5.3.1 Read
      • 5.3.2 Write
        • 5.3.2.1 Four-Byte Write
        • 5.3.2.2 Internal Read-Modify-Write
      • 5.3.3 Exchange Cycle
      • 5.3.4 Refresh
      • 5.3.5 ECC Initialization
      • 5.3.6 Configuration Circuitry
  • Chapter 6 Address Buffer and Data Buffer Modules
    • 6.1 General Description
    • 6.2 Address Buffer Module (M8158)
      • 6.2.1 Main Memory Bus Interface
      • 6.2.2 Address Parity Checking
      • 6.2.3 Address Modification
    • 6.3 Data Buffer Module (M8159)
      • 6.3.1 Main Memory Bus Interface
      • 6.3.2 Control and Status Register
      • 6.3.3 Control and Status Bit Allocation
      • 6.3.4 CSR Addressing
  • Chapter 7 Power Supply and Distribution
    • 7.1 General Description
    • 7.2 Power Supply Cables
      • 7.2.1 External Power Cables
      • 7.2.2 Internal Power Harnesses
    • 7.3 Power Supply Major Assemblies
      • 7.3.1 Power Controller (861-D, E)
      • 7.3.2 AC Input Box (7009811-1, 2)
      • 7.3.3 Transformer Assembly (7011486)
      • 7.3.4 +5 Vdc Regulator (H7441)
      • 7.3.5 ±12 VB and +5 VB Battery Backup Regulators (7014251) and Battery Backup Units (H775D)
    • 7.4 Power Distribution
    • 7.5 Voltage Measurements and Adjustments
      • 7.5.1 H7441 Voltage Regulator Adjustment, +5 V
      • 7.5.2 7014251 Voltage Regulator Adjustment, ±12 VB and +5 VB
    • 7.6 Power Supply Subassembly Removal Procedure
      • 7.6.1 Power Supply Access Procedure
      • 7.6.2 H7441 and 7014251 Regulator Replacement (Removal and Installation)
      • 7.6.3 AC Input Box and 5411086-YA Power Line Monitor Board
      • 7.6.4 Fan Removal
      • 7.6.5 Transformer Assembly Removal
  • Chapter 8 Installation
    • 8.1 Introduction
    • 8.2 Adding Array Modules
    • 8.3 Adding a Memory to an Existing Memory Cabinet
    • 8.4 Installing Second Memory Cabinet
  • Chapter 9 Maintenance
    • 9.1 Introduction
    • 9.2 Diagnostic Program
      • 9.2.1 Operating Instructions
      • 9.2.2 Console Switch Register Options
      • 9.2.3 Memory Configuration Map
      • 9.2.4 Error Printout
      • 9.2.5 Field Service Mode
    • 9.3 Troubleshooting
    • 9.4 Test Procedure For ECC Initialization and Boot Characteristics
  • Appendix A MOS Chip Description
    • A.1 Physical Description
    • A.2 Functional Description
      • A.2.1 The Cell Storage Element
      • A.2.2 Read, Write, and Refresh
      • A.2.3 Timing
  • Appendix B MK11 Memory System Block Diagram
  • Appendix C MK11 Memory Timing Diagrams

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