PDP-11/84 System Installation and Technical Reference Manual (Preliminary)

Company:Digital Equipment Corporation
Part:EK-1184A-TM-PR2
Date:1985-05
Keywords:

Table of Contents

  • Chapter 1 System Introduction
    • 1.1 Introduction
    • 1.2 System Components and Variations
      • 1.2.1 KDJ11-BF Processor Module
      • 1.2.2 KTJ11-B UNIBUS Adapter Module
      • 1.2.3 MSV11-JB/JC Memory Module
      • 1.2.4 UNIBUS Terminator
      • 1.2.5 Monitor and Distribution Module
      • 1.2.6 Minimum Load Module
      • 1.2.7 Power Supply
      • 1.2.8 Console Serial Line Board
      • 1.2.9 Backplane Assembly
      • 1.2.10 Front Panel Assembly
      • 1.2.11 Cabinet Power Controller
      • 1.2.12 Cabinet Blower Unit
      • 1.2.13 Box Cooling Fans
      • 1.2.14 Additional Expansion and Memory Options
    • 1.3 System Specifications
    • 1.4 Related Documents
  • Chapter 2 Site Preparation and Installation
    • 2.1 Site Preparation
      • 2.1.1 Cabinet Site Preparation
      • 2.1.2 Box Site Preparation
    • 2.2 Shipping Specifications
    • 2.3 Unpacking Instructions
      • 2.3.1 Cabinet Unpacking
      • 2.3.2 Box Unpacking
    • 2.4 System Installation
      • 2.4.1 Cabinet Mechanical Installation
      • 2.4.2 Box Mechanical Installation
      • 2.4.3 Console Serial Line Hookup
      • 2.4.4 Cabinet Switch Settings
      • 2.4.5 Box Switch Settings
      • 2.4.6 Cabinet Power Hookup
      • 2.4.7 Box Power Hookup
    • 2.5 System Controls and Indicators
      • 2.5.1 Front Panel
      • 2.5.2 Console Serial Line Distribution Board
      • 2.5.3 Serial Communications Port
      • 2.5.4 Baud Rate Select Switch
    • 2.6 System Hardware Configuration
      • 2.6.1 KDJ11-BF Module Configuration
      • 2.6.2 KTJ11-B Module Configuration
      • 2.6.3 Monitor and Distribution Module Configuration
      • 2.6.4 MSV11-JB/JC Module Configuration
      • 2.6.5 Minimum Load Module
    • 2.7 Expansion Backplane Installation
      • 2.7.1 Expansion Backplane Installation
      • 2.7.2 NPG and BG Jumper Load Routing
      • 2.7.3 Backplane Power Connections
      • 2.7.4 SPC Backplane Locations
    • 2.8 SPC Module Installation
      • 2.8.1 Cabinet SPC Cable Routing
      • 2.8.2 Box SPC Cable Routing
    • 2.9 Cabinet Battery Backup Unit Installation
    • 2.10 Box Battery Backup Unit Installation
  • Chapter 3 Functional Description
    • 3.1 Introduction
    • 3.2 PMI Bus Description
      • 3.2.1 PMI Bus Acquisition
      • 3.2.2 DMA Requests
      • 3.2.3 UNIBUS Device Interrupt Requests
      • 3.2.4 PMI Data Transfer Address Cycle
      • 3.2.5 PMI Data Transfer Protocol
      • 3.2.6 PMI Data In Cycles (DATI) and (DATIP)
      • 3.2.7 PMI Block Mode Data In Cycles
      • 3.2.8 PMI Data Out Cycles
    • 3.3 Memory Management
      • 3.3.1 Page Address Registers
      • 3.3.2 Page Descriptor Registers
      • 3.3.3 Memory Management Register 0
      • 3.3.4 Memory Management Register 1
      • 3.3.5 Memory Management Register 2
      • 3.3.6 Memory Management Register 3
      • 3.3.7 Physical Address Construction
      • 3.3.8 Memory Relocation
    • 3.4 KDJ11-BF Cache
      • 3.4.1 KDJ11-BF Cache Operations
      • 3.4.2 KDJ11-BF Cache Organization
      • 3.4.3 Cache Control Register
      • 3.4.4 Memory System Error Register
      • 3.4.5 Hit/Miss Register
    • 3.5 Additional CPU Register Descriptions
      • 3.5.1 Processor Status Word
      • 3.5.2 Program Interrupt Request Register
      • 3.5.3 CPU Error Register
      • 3.5.4 Configuration and Display Register
      • 3.5.5 Maintenance Register
      • 3.5.6 Boot and Diagnostic Controller Status Register
      • 3.5.7 Page Control Register
      • 3.5.8 Line Frequency Clock and Status Register
    • 3.6 Stack Limit Protection
    • 3.7 Kernel Protection
    • 3.8 Trap and Interrupt Service Priorities
    • 3.9 Console Serial Line Unit
      • 3.9.1 Receiver Status Register
      • 3.9.2 Receiver Data Buffer
      • 3.9.3 Transmitter Receiver Status Register
      • 3.9.4 Transmitter Data Buffer Register
      • 3.9.5 Break Response
    • 3.10 Kernel/Supervisor/User Mode Descriptions
    • 3.11 PMG Counter
    • 3.12 KTJ11-BF Cache Operations
      • 3.12.1 KTJ11-B Cache Organization
      • 3.12.2 DMA Cache Enable/Disable
      • 3.12.3 DMA Cache Write Operations
      • 3.12.4 DMA Cache Read Operations
    • 3.13 UNIBUS Mapping
      • 3.13.1 UNIBUS Mapping Registers
      • 3.13.2 Optional UNIBUS Memory
      • 3.13.3 Memory Configuration Register
    • 3.14 Diagnostic and Configuration Registers
      • 3.14.1 Diagnostic Controller Status Register
      • 3.14.2 Diagnostic Data Register
      • 3.14.3 Diagnostic DATI NPR Cycles
      • 3.14.4 Diagnostic DATO NPR Cycles
  • Chapter 4 Bootstrap and Diagnostic ROM Programming
    • 4.1 Introduction
    • 4.2 Dialog Mode Command Descriptions
      • 4.2.1 Help Command
      • 4.2.2 Boot Command
      • 4.2.3 List Command
      • 4.2.4 Setup Command
      • 4.2.5 Map Command
      • 4.2.6 Test Command
    • 4.3 Setup Mode Command Descriptions
      • 4.3.1 Setup Command 1
      • 4.3.2 Setup Command 2
      • 4.3.3 Setup Command 3
      • 4.3.4 Setup Command 4
      • 4.3.5 Setup Command 5
      • 4.3.6 Setup Command 6
      • 4.3.7 Setup Command 7
      • 4.3.8 Setup Command 8
      • 4.3.9 Setup Command 9
      • 4.3.10 Setup Command 10
      • 4.3.11 Setup Command 11
      • 4.3.12 Setup Command 12
      • 4.3.13 Setup Command 13
      • 4.3.14 Setup Command 14
      • 4.3.15 Setup Command 15
    • 4.4 Diagnostic Error Messages
    • 4.5 Bootstrap Programs
      • 4.5.1 Bootstrap List
      • 4.5.2 EEPROM Format
      • 4.5.3 General Rules For EEPROM User Boots
    • 4.6 Boot ROM Facility (M9312 Compatible)
      • 4.6.1 Boot ROM Installation
      • 4.6.2 ROM Addresses
      • 4.6.3 ROM Formats
      • 4.6.4 Single ROM Programs
      • 4.6.5 Multiple ROM Programs
      • 4.6.6 Program Headers
      • 4.6.7 ROM Data Organization
    • 4.7 J11 Micro ODT
      • 4.7.1 / (ASCII 057) Slash
      • 4.7.2 <CR> (ASCII 015) Carriage Return
      • 4.7.3 <LF> (ASCII 012) Line Feed
      • 4.7.4 $ (ASCII 122) Internal Register Designator
      • 4.7.5 G (ASCII 107) GO
      • 4.7.6 P (ASCII 120) Proceed
      • 4.7.7 ^S (Control-Shift-S) Binary Dump
  • Chapter 5 System Maintenance
    • 5.1 Introduction
    • 5.2 Diagnostic Types
    • 5.3 Console Terminal Error Message Format
      • 5.3.1 Console Error Message Description
      • 5.3.2 Unexpected Trap and MMU Error Code Descriptions
      • 5.3.3 Boot Program Error Codes/Messages
    • 5.4 System Troubleshooting Aids
      • 5.4.1 Front Panel
      • 5.4.2 MDM Module
      • 5.4.3 KDJ11-BF CPU Module
      • 5.4.4 MSV11-JB/JC Memory Module
      • 5.4.5 KTJ11-B UBA Module
      • 5.4.6 Minimum Load Module
    • 5.5 Field Replaceable Units
    • 5.6 Module Replacement/Removal Procedures
      • 5.6.1 General Module Removal/Replacement
      • 5.6.2 CPU Module Removal/Replacment
    • 5.7 Power Supply Removal/Replacement
      • 5.7.1 Cabinet Power Supply Removal/Replacement
      • 5.7.2 Box Power Supply Removal/Replacement
    • 5.8 Cabinet Blower Removal/Replacement
    • 5.9 Box Fan Removal/Replacement
    • 5.10 Front Panel Removal/Replacement
      • 5.10.1 Cabinet Front Panel Removal/Replacement
      • 5.10.2 Box Front Panel Removal/Replacement
    • 5.11 Circuit Breaker Removal/Replacement
      • 5.11.1 Cabinet Circuit Breaker Removal/Replacement
      • 5.11.2 Box Circuit Breaker Removal/Replacement
    • 5.12 Cabinet Power Controller Removal/Replacement
    • 5.13 SLU Interface Assembly Removal/Replacement
      • 5.13.1 Cabinet SLU Assembly Removal/Replacement
      • 5.13.2 Box SLU Assembly Removal/Replacement
    • 5.14 CPU Backplane Removal/Replacement
      • 5.14.1 Cabinet Backplane Removal
      • 5.14.2 Box Backplane Removal
    • 5.15 Cabinet Peripheral Access
  • Appendix A CPU Instruction Timing
    • A.1 Introduction
    • A.2 Source and Destination Table Notes
  • Appendix B PDP-11/84 Hardware/Software Differences
    • B.1 UNIBUS Power Up Protocol Differences
    • B.2 PDP-11/84 -- 11/44 Hardware Differences
    • B.3 PDP-11/94 -- 11/70 Hardware Differences
    • B.4 Software Differences
  • Appendix C Pinout Backplane Test Connectors J18 and J19
  • Appendix D Backplane Pin Assignments
  • Appendix E System Interconnect Diagram
  • Appendix F V.7 -- V.6 ROM Code Differences
    • F.1 Introduction
    • F.2 Boot Support for Tape MSCP Devices (TU81)
    • F.3 V7.0 Disable Setup Mode Parameter
    • F.4 V7.0 Disable All Testing Parameter
    • F.5 B Mnemonic for ROM Boots
    • F.6 Edit/Create Command
    • F.7 Trap To Location 4
    • F.8 Disk MSCP Auto Boot Routine
    • F.9 Disk MSCP Boot Differences
    • F.10 Initialize Command
    • F.11 Memory Testing
    • F.12 Power Up Or Restart Mode Set To 3
    • F.13 Power Up Set To 3 With Battery Backup
    • F.14 Enabling Halt On Break
    • F.15 Ctrl R and Ctrl U Echoing
    • F.16 Setup Command 5
    • F.17 Automatic Boot Sequence Message
    • F.18 Boot Command List Addition
    • F.19 Local Language Support
    • F.20 Additional Map Command Feature
  • Appendix G Multi Boot ROM Control Transfer
    • G.1 Introduction
    • G.2 Transfer Control Program
    • G.3 EEPROM Load Example
  • Appendix H Configuration Register Modification
    • H.1 Introduction
    • H.2 ROM Code Interpretation
  • Appendix I Floating Point Instruction Timing
  • Appendix J Set-Up Parameter Worksheets

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