PDP-8/I Maintenance Manual Volume I

Company:Digital Equipment Corporation
Part:DEC-8I-HR1A-D
Date:1970-03
Keywords:PDP-8/I

Table of Contents

  • Chapter 1 Introduction and Description
    • 1.1 Introduction
    • 1.2 Description
    • 1.3 Pertinent Documents
    • 1.4 Abbreviations
  • Chapter 2 Installation
    • 2.1 Space Requirements
    • 2.2 Environmental Requirements
    • 2.3 Power Requirements
    • 2.4 Cable Requirements
    • 2.5 Installation Procedure
    • 2.6 Internal Option Installation
    • 2.7 System Configurations
    • 2.8 I/O Interface
      • 2.8.1 I/O Bus Signal
      • 2.8.2 I/O Cables
      • 2.8.3 Logic Levels and Level Converters
      • 2.8.4 Interface Signal Connections
  • Chapter 3 Operation
    • 3.1 Controls and Indicators
      • 3.1.1 Computer
      • 3.1.2 Teletype
    • 3.2 Operating Procedures
      • 3.2.1 Common Procedures
      • 3.2.2 Manual Loading Procedures
      • 3.2.3 Teletype Loading Procedures
      • 3.2.4 Off-Line Teletype Procedures
  • Chapter 4 Theory
    • Section I Block Diagram Discussion
    • 4.1 Registers
      • 4.1.1 Accumulator (AC)
      • 4.1.2 Link (L)
      • 4.1.3 Program Counter (PC)
      • 4.1.4 Memory Address Register (MA)
      • 4.1.5 Memory Buffer Register (MB)
      • 4.1.6 Sense Register (SENSE or MEM)
      • 4.1.7 Instruction Register (IR)
      • 4.1.8 Switch Register (SR)
    • 4.2 Major Register Gating Network
    • 4.3 Timing and Control Elements
      • 4.3.1 Timing Elements
      • 4.3.2 Control Elements
    • 4.4 Input/Output
    • 4.5 Memory
      • 4.5.1 Core Array
      • 4.5.2 Memory Control
      • 4.5.3 Address Selection
      • 4.5.4 Inhibit Drivers
      • 4.5.5 Sense Amplifiers
    • Section II General Theory
    • 4.6 Time States/Time Pulses
    • 4.7 Major States
    • 4.8 Internal Data Flow
    • 4.9 Instructions
      • 4.9.1 Memory Reference Instructions
      • 4.9.2 Augmented Instructions
    • 4.10 Program Interrupt
      • 4.10.1 Instructions
    • Section III Detailed Memory Theory
    • 4.11 Overall Memory Theory
    • 4.12 Memory Operation
      • 4.12.1 Memory Control
      • 4.12.2 Read/Write
      • 4.12.3 Address Selection
    • Section IV Detailed Processor Theory
    • 4.13 Flow Diagram Interpretation
    • 4.14 Timing
      • 4.14.1 Manual Function Timing Generator
      • 4.14.2 Manual Operations
      • 4.14.3 Time States
    • 4.15 Major States
    • 4.16 Internal Data Flow
      • 4.16.1 Source
      • 4.16.2 Route
      • 4.16.3 Destination
    • 4.17 Operating Instructions
      • 4.17.1 Instructions
      • 4.17.2 Memory Reference Instructions
      • 4.17.3 Direct/Indirect Addressing
      • 4.17.4 Augmented Instructions
  • Chapter 5 Maintenance
    • 5.1 Equipment
    • 5.2 Programs
    • 5.3 Preventive Maintenance
      • 5.3.1 Weekly Checks
      • 5.3.2 Preventive Maintenance Tools
    • 5.4 Corrective Maintenance
      • 5.4.1 Preliminary Investigation
      • 5.4.2 System Troubleshooting
      • 5.4.3 Logical Troubleshooting
      • 5.4.4 Circuit Troubleshooting
      • 5.4.5 Repairs and Replacement
      • 5.4.6 Validation Tests
      • 5.4.7 Recording
    • 5.5 Adjustments
      • 5.5.1 Power-Up Threshold Adjustment
      • 5.5.2 Memory Alignment Procedure
    • 5.6 ASR33 Teleprinter and Control Maintenance
      • 5.6.1 Equipment
      • 5.6.2 Programs
      • 5.6.3 Preventive Maintenance
      • 5.6.4 Corrective Maintenance
    • 5.7 Spare Parts
    • 5.8 Mechanization Charts

Copies

Address: http://bitsavers.org/pdf/dec/pdp8/pdp8i/DEC-8I-HR1A-D_8Imaint_Mar70.pdf
Site: Al Kossow's Bitsavers
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MD5: 97b6b9741d4819e9443c5f0349171032
Mirrors:
 
Address: http://highgate.comm.sfu.ca/pdp8/pdp8i-docs/dec-8i-hr1a-d.tif
Site: Kevin McQuiggin's PDP-8 page at Highgate
Format: TIFF
Size: 5713396 bytes (5.4 MiB)
MD5: 5203a7fc019b9e39c4aef8d8ee1233df
Notes: Fourth printing, July 1969