Guest |
Login
version 2.0.7
Manx – a catalogue of online computer manuals
Search
News
About
Help
KS10-Based DECSYSTEM-2020 Technical Manual
Company:
Digital Equipment Corporation
Part:
EK-0KS10-TM-002
Date:
1979-09
Keywords:
Table of Contents
Chapter 1
Overview
1.1
Introduction
1.2
System Hardware
1.3
KS10 Physical Description
1.3.1
KS10-PA Card Cage
1.3.2
BA11-K Unibus Option Drawer
1.3.3
Power System
1.3.4
Massbus Transition Plate
1.3.5
Asynchronous Terminal Distribution Panel (H317-E)
1.3.6
Operator's Switch Panel
1.4
DNHXX Physical Description
Chapter 2
Site Preparation and Planning
2.1
Site Planning
2.2
Environmental Requirements
2.3
System Cabling
2.4
Primary Power (AC)
2.5
Option Data Sheets
Chapter 3
Installation
Chapter 4
Operation/Programming
4.1
Controls and Indicators
4.2
Instruction Set
4.3
Number System
4.4
Effective Address Calculation
4.5
Machine Modes
4.6
Process Tables
4.7
Memory Address Mapping by the CPU
4.8
Memory Address Mapping by the UBA
4.9
General-Purpose Register Blocks
4.10
Memory System
4.11
Priority Interrupt System
4.12
KS10 Processor Status Words
4.13
Operator Console
4.14
Remote Diagnosis (KLINIK) Line
Chapter 5
Technical Description
5.1
Introduction
5.1.1
Console
5.1.2
CPU
5.1.3
MOS Memory
5.1.4
Unibus Adapter
5.2
System Timing
5.2.1
Basic Clocks
5.2.2
CPU Clock Control
5.3
KS10 (Backplane) Bus
5.3.1
8646 Bus Transceiver
5.3.2
Bus Arbitration
5.3.3
Bus Usage
5.3.4
Command/Address Cycle
5.3.5
Bus Memory Operation
5.3.6
Bus I/O Operation
5.3.7
Bus PI Operation
5.3.8
Diagnostic Operations
5.3.9
Bus Parity Error
5.4
Microcontroller
5.4.1
Microword
5.4.2
Dispatch Word
5.4.3
Control RAM
5.4.4
Skip and Dispatch Logic
5.4.4.1
Dispatch ROM
5.4.4.2
Other Dispatch Procedures
5.4.5
Subroutine Stack
5.4.6
Booting and Diagnosis
5.5
Data Path Execute
5.5.1
Arithmetic Unit
5.5.2
Main Path
5.5.3
RAM File
5.5.4
Ten-Bit Logic
5.5.5
Program Flags
5.6
Data Path Memory
5.6.1
Memory and I/O Setup
5.6.2
Bus Operation
5.6.3
Paging
5.6.4
Cache
5.6.5
Error Logic
5.6.6
Priority Interrupt
5.7
Memory
5.7.1
Storage Organization and Addressing
5.7.2
MOS Data Bus
5.7.3
Command/Address Load (Memory Access)
5.7.4
Memory Write
5.7.5
Memory Read
5.7.6
Read-Pause-Write
5.7.7
Error Detection and Correction
5.7.8
Status Read/Write
5.7.9
Refresh Cycle
5.8
Console
5.8.1
8080 Console Processor
5.8.1.1
8080A Timing
5.8.1.2
8080A Operation
5.8.1.3
Console Operations
5.8.2
CPU/Bus Control
5.8.2.1
KS10 Bus Functions
5.8.2.2
Instruction Register Read Operation
5.8.3
Console Program
5.8.3.1
Power-Up/Initialization
5.8.3.2
Console Commands
5.8.3.3
System Bootstrap
5.9
Unibus Adapter
5.9.1
Basic Operation
5.9.1.1
NPR Data Transfers
5.9.1.2
I/O Register Data Transfers
5.9.1.3
PI Operation
5.9.2
UBA Status and Control Registers
5.9.2.1
Paging RAM
5.9.2.2
Status Register
5.9.2.3
Maintenance Register
5.9.3
Logical Operation
5.9.4
NPR Data Transfer Operation
5.9.5
I/O Data Transfer Operation
5.9.6
PI Operation
5.9.7
Wraparound Data Transfer
5.10
KS10 Power System
5.10.1
861 Power Controller
5.10.2
H7130 Power Supply and 5413261 Power Distribution Module
5.10.3
H765 Power Supply (BA11-K)
Appendix A
KS10 Differences (KS10 vs. KL10)
Appendix B
KS10 Unibus
Appendix C
Microcode Operation
Copies
Address:
http://bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
Site:
Al Kossow's Bitsavers
Format:
PDF
Size:
14768499 bytes (14.1 MiB)
MD5:
25b105996f821e2facd9dd620c7a910e
Mirrors:
http://bitsavers.trailing-edge.com/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
http://www.bighole.nl/pub/mirror/www.bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
http://www.textfiles.com/bitsavers/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
http://www.mirrorservice.org/sites/www.bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
ftp://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf
ftp://ftp.mirrorservice.org/sites/www.bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf