VAX 8530/8550/8700/8800 System Maintenance Guide

Company:Digital Equipment Corporation
Part:EK-88XVS-KT-001
Date:1987-08
Keywords:

Table of Contents

  • Section 1 System Architecture
  • Chapter 1 The Physical System
    • 1.1 Manual Scope
    • 1.2 Manual Organization
    • 1.3 System Cabinet Layout
    • 1.4 Kernel Block Diagram
    • 1.5 Cabinet Layout (Rear View)
    • 1.6 Module Identification
    • 1.7 Power System Module Identification
    • 1.8 Module Layout
    • 1.9 System Jumpers
      • 1.9.1 Revision Jumpers
      • 1.9.2 Serial Number Jumpers
    • 1.10 Backplane Pins
    • 1.11 F-Series Pins
  • Chapter 2 System Mapping and Device Memory Allocation
    • 2.1 Virtual Memory Addressing
    • 2.2 Physical Address Map
    • 2.3 NMI Address Selection
    • 2.4 System Control Block
  • Section 2 Hardware
  • Chapter 3 Hardware Reference Documentation
  • Chapter 4 Cables, Jumpers, and Revision Control
    • 4.1 CPU Backplane Assembly
    • 4.2 Cabinet Assembly (Front View)
    • 4.3 Cabinet Assembly (Side View)
    • 4.4 Cabinet Assembly (Rear View)
    • 4.5 Cabinet Assembly (Cable Installation)
    • 4.6 CPU Backplane Connections
    • 4.7 Parts List
    • 4.8 NBI Cables to VAXBI Backplanes
  • Chapter 5 Power System Complex
    • 5.1 VAX 8700/8800 System Circuit Breakers
    • 5.2 Upper Power Rack
    • 5.3 Power Distribution
    • 5.4 Console Cabling
    • 5.5 Power-Up Sequence
    • 5.6 Power Up From BBU
    • 5.7 Power-Down Sequence
    • 5.8 Power Down/Power Interrupt With BBU
    • 5.9 Console/EMM Power Up
    • 5.10 Console/EMM Power Down
    • 5.11 Console/EMM Power Failure
    • 5.12 H7170 LEDs and Error Codes
    • 5.13 MPS LEDs and Error Codes
    • 5.14 EMM LEDs and Error Codes
    • 5.15 Power/Environmental System
      • 5.15.1 Module Placement Verification
      • 5.15.2 Module Key Test
      • 5.15.3 Module Key Test Block Diagram
      • 5.15.4 Module Key Test Connections
      • 5.15.5 Module Placement
    • 5.16 Power Monitoring/Error Reporting
      • 5.16.1 Default Mode Error Reporting
      • 5.16.2 Operational Error Handling
    • 5.17 Power System Circuit Breakers
    • 5.18 Power System Connectors
    • 5.19 Power System MPS Backplane Connectors
    • 5.20 Console Power Connectors
    • 5.21 NBOX Port Conditioner (Front View)
  • Chapter 6 Kernel Diagrams and Interconnects
    • 6.1 VAX 8700/8800 System Block Diagram
    • 6.2 Console Block Diagram
    • 6.3 Console Interface
    • 6.4 Clock Module Block Diagram
    • 6.5 CPU Block Diagram
    • 6.6 IBox Block Diagram
    • 6.7 EBox Block Diagram
    • 6.8 CBox Block Diagram
    • 6.9 MBox Block Diagram
    • 6.10 I/O Interconnects and Adapters
    • 6.11 NMI Signals and Timing
    • 6.12 NMI Signals
    • 6.13 NMI Signals Descriptions
    • 6.14 NMI Write Transaction
    • 6.15 NMI Read Transaction
    • 6.16 NMI Write Transaction Types
    • 6.17 NMI Read Transaction Types
    • 6.18 Detailed NMI Arbitration Line Timing
    • 6.19 Memory Busy Timing
    • 6.20 Fault Signal Timing
  • Chapter 7 Register Descriptions
    • 7.1 Console-to-VAX Data/Status/Control Registers
    • 7.2 VAX-to-Console Data/Status/Control Registers
    • 7.3 Real-Time Interface
    • 7.4 VAX Architectural IPRs
      • 7.4.1 Stack Pointers
      • 7.4.2 P0/P1 Base Registers
      • 7.4.3 System Base Register
      • 7.4.4 P0/P1/System Length Registers
      • 7.4.5 Process Control Block Base
      • 7.4.6 System Control Block Base
      • 7.4.7 Interrupt Priority Level
      • 7.4.8 Asynchronous System Trap (AST) Level
      • 7.4.9 Software Interrupt Request
      • 7.4.10 Software Interrupt Summary
      • 7.4.11 Memory Management Enable
      • 7.4.12 Translation Buffer Invalidate All
      • 7.4.13 Translation Buffer Invalidate Single
    • 7.5 Machine Specific IPRs
      • 7.5.1 Machine Check Status
      • 7.5.2 Performance Monitor Enable
      • 7.5.3 System Identification
      • 7.5.4 Cache On
      • 7.5.5 Revision Register 1
      • 7.5.6 Revision Register 2
    • 7.6 NMI Registers
      • 7.6.1 NMI Interrupt Control
      • 7.6.2 NMI Fault Summary
      • 7.6.3 NMI Silo Data
      • 7.6.4 NMI Error Address
      • 7.6.5 Interrupt Other Processor
    • 7.7 I/O Register Space Addressing
      • 7.7.1 Node ID and Window Space Address
      • 7.7.2 I/O Registers in NBI and Memory Controller
    • 7.8 NBI Registers
      • 7.8.1 NBIA Control/Status Register 0 (CSR0)
      • 7.8.2 NBIA Control/Status Register 1 (CSR1)
      • 7.8.3 NBIA BR4 Vector Register (BR4VR)
      • 7.8.4 NBIA BR5 Vector Register (BR5VR)
      • 7.8.5 NBIA BR6 Vector Register (BR6VR)
      • 7.8.6 NBIA BR7 Vector Register (BR7VR)
      • 7.8.7 NBIB Registers
      • 7.8.8 NBIB Device Type Register (R/W, DMW, DCLOL)
      • 7.8.9 NBIB Control and Status Register
      • 7.8.10 NBIB Bus Error Register (W1C, DCLOC)
      • 7.8.11 NBIB Error Interrupt Control Register
      • 7.8.12 NBIB Interrupt Destination Register (R/W, DCLOC)
      • 7.8.13 NBIB IP Interrupt Mask Register (R/W, DCLOC)
      • 7.8.14 NBIB IP Interrupt Destination Register (R/W, DCLOC)
      • 7.8.15 NBIB IP Interrupt Source Register (W1C, DCLOC)
      • 7.8.16 NBIB Starting Address Register (R/W, DCLOC)
      • 7.8.17 NBIB Ending Address Register (R/W, DCLOC)
      • 7.8.18 NBIB BCI Control Register
      • 7.8.19 NBIB Write Status Register (W1C, DCLOC)
      • 7.8.20 NBIB User Interrupt Control Register
    • 7.9 MCL Control and Status Registers
    • 7.10 Maintenance Aids
      • 7.10.1 VBus Directory
      • 7.10.2 CBox Error Register -- IPR A0
      • 7.10.3 IBox Error Register -- IPR C0
      • 7.10.4 EBox Error Register -- IPR B0
    • 7.11 EMM Registers
    • 7.12 UET Setup
  • Section 3 Console Subsystem
  • Chapter 8 Console Software
    • 8.1 Required Components (Hardware/Software)
    • 8.2 Required Components (Console Software)
  • Chapter 9 Start-Up and Initialization
    • 9.1 Console Power-Up Flow
    • 9.2 The Big Picture
    • 9.3 Loading and Access Registers
    • 9.4 Miscellaneous Registers
    • 9.5 PPI Control Word Register
    • 9.6 Port Formats
    • 9.7 RXDB/TXDB Formats
    • 9.8 Control Registers 0, 1, 2
    • 9.9 Firmware Load Path
    • 9.10 Power-Up Procedure
      • 9.10.1 EMM Power-Up
        • 9.10.1.1 EMM Errors
        • 9.10.1.2 EMM Default Parameters
        • 9.10.1.3 EMM Response to Console Commands
      • 9.10.2 Console (PRO) Power-Up and Initialization
        • 9.10.2.1 Boot PRO38N Operating System/Run Console
        • 9.10.2.2 Initialize Console Database
        • 9.10.2.3 Spawn RTI Driver
        • 9.10.2.4 Test EMM Communications and Read EMM Revision Number
        • 9.10.2.5 Check EMM Software Revision Number/Test for Compatibility
        • 9.10.2.6 Program EMM with VAX 8800 Environmental Parameters
        • 9.10.2.7 Unlock/Open Logfile
        • 9.10.2.8 Reconstruct Console State
        • 9.10.2.9 Test for Previous System INIT in Progress Flag
        • 9.10.2.10 Test VAX 8800 Power Status
        • 9.10.2.11 Set System INIT in Progress Flag
        • 9.10.2.12 Force @SYSINIT.COM into Console Command Stream
        • 9.10.2.13 System Initialization (SYSINIT.COM)
      • 9.10.3 Summary of SYSINIT.COM
  • Section 4 Microcode
  • Chapter 10 Microcode Charts
    • 10.1 Microcode Overview
    • 10.2 CS0 Segment Chart
    • 10.3 CS1 Segment Chart
    • 10.4 CS2 Segment Chart
  • Chapter 11 Entry Point Microaddress Formats
    • 11.1 Field Definitions/Operand Specifier Entry
    • 11.2 Field Definitions/Instruction Entry
    • 11.3 Field Definitions/Trap Addresses
    • 11.4 Entry Point Label Definitions/Macros
      • 11.4.1 Field Definitions/Special Addresses
      • 11.4.2 Field Definitions/Hardcoded Addresses
      • 11.4.3 Macro Definitions/Operand Specifier and Instruction Entry
      • 11.4.4 Macro Definitions/Trap and Special Addresses
      • 11.4.5 Macro Definitions/Hardcoded Addresses
  • Chapter 12 Interrupts and Exceptions
    • 12.1 IE/Execute Microcode Protocol
    • 12.2 Vectors
    • 12.3 VAXBI NBIA 0 Vectors (No UNIBUS)
    • 12.4 VAXBI NBIA 1 Vectors (No UNIBUS)
    • 12.5 UNIBUS Vectors
    • 12.6 VAXBI NBIA 0 Vectors (Two UNIBUSs)
    • 12.7 VAXBI NBIA 1 Vectors (Two UNIBUSs)
  • Chapter 13 Console Support Microcode
    • 13.1 Console Support Microcode Entry Points
    • 13.2 Console Support Microcode Commands
    • 13.3 Console Support Microcode Initialization
      • 13.3.1 Micromachine and VAX Initialization
      • 13.3.2 Micromachine Initialization
      • 13.3.3 Initializing Memory Subsystem
      • 13.3.4 Initializing Translation Buffer
      • 13.3.5 Initializing Cache
      • 13.3.6 Initializing Processor Registers
    • 13.4 Console Support Microcode -- Registers
      • 13.4.1 Architectural Processor Registers
      • 13.4.2 VAX 8800 Specific Internal Processor Registers
      • 13.4.3 VAX 8800 Microcode-Visible Registers
      • 13.4.4 Processor Registers Initialized by Microcode
        • 13.4.4.1 Stack Pointers
        • 13.4.4.2 Mapping Registers
        • 13.4.4.3 Control Block Registers
        • 13.4.4.4 IPL/PSL
        • 13.4.4.5 ASTLVL
        • 13.4.4.6 SIRR
        • 13.4.4.7 SISR
        • 13.4.4.8 Interval Timer Registers
        • 13.4.4.9 TODR
        • 13.4.4.10 Console Communication Registers
        • 13.4.4.11 Memory Management
        • 13.4.4.12 Translation Buffer Registers
        • 13.4.4.13 Performance Monitor
        • 13.4.4.14 SID
        • 13.4.4.15 NMIIC
        • 13.4.4.16 CCR
        • 13.4.4.17 MCSTS
        • 13.4.4.18 REVR1, REV2
        • 13.4.4.19 CIOP
        • 13.4.4.20 IBox Error Register
        • 13.4.4.21 EBox Error Register
        • 13.4.4.22 CBox Error Register
        • 13.4.4.23 Diagnostic Control Register
  • Section 5 Software
  • Chapter 14 VMS Library
  • Chapter 15 System Boot Procedures
    • 15.1 Overview
    • 15.2 Restart/Boot/Halt Flow
    • 15.3 Detailed Boot Process
    • 15.4 Software Switches (Boot Flags)
    • 15.5 Boot Control Flags
      • 15.5.1 BCIBOO.COM
      • 15.5.2 BDABOO.COM
      • 15.5.3 DEFBOO.COM
      • 15.5.4 RESTAR.COM
      • 15.5.5 SECBOO.COM
      • 15.5.6 SYSINIT.COM
    • 15.6 VMB.EXE Header Information
    • 15.7 VAX 8800 Specific VMB Components
    • 15.8 VMB.EXE Primary Bootstrap Error Messages
    • 15.9 VMB Bad Page Mapping Memos
  • Chapter 16 System Error Gathering
    • 16.1 VAXBI Error Entry
    • 16.2 Machine Check Entry
    • 16.3 Uncorrectable Memory Error Entry
    • 16.4 Correctable Memory Error Entry
    • 16.5 NMI Fault Entry
    • 16.6 Console Timeout Entry
    • 16.7 EMM Entry
  • Section 6 Diagnostics and Maintenance
  • Chapter 17 Diagnostic Hierarchy
    • 17.1 Diagnostic Overview
      • 17.1.1 General
      • 17.1.2 Bottom-Up Testing
    • 17.2 Diagnostics
      • 17.2.1 Console Self-Test
      • 17.2.2 Microdiagnostics
      • 17.2.3 Micromonitor Commands
        • 17.2.3.1 Continue Command
        • 17.2.3.2 Diagnose Command
        • 17.2.3.3 Exit Command
        • 17.2.3.4 Load Command
        • 17.2.3.5 Loop Command
        • 17.2.3.6 Select Command
        • 17.2.3.7 Set/Clear Flags Commands
        • 17.2.3.8 Verify Module Command
    • 17.3 VAX 8800 Microdiagnostics Breakdown
    • 17.4 Sample Diagnostic Using the Micromonitor
    • 17.5 Diagnostic/Module Cross Reference
      • 17.5.1 EZKAA
      • 17.5.2 EZKAB
      • 17.5.3 EZKAC
      • 17.5.4 EZKAD
      • 17.5.5 EZKAE
      • 17.5.6 EZKAF
      • 17.5.7 EZKAH
      • 17.5.8 EZKAJ
      • 17.5.9 EZKAK
      • 17.5.10 EZKAL
      • 17.5.11 EZKAM
      • 17.5.12 EZKAN
      • 17.5.13 EZKAP
      • 17.5.14 EZKAR
      • 17.5.15 EZKAS
      • 17.5.16 EZKAT
      • 17.5.17 EZKAU
      • 17.5.18 EZKAV
      • 17.5.19 EZKAW
      • 17.5.20 EZKAY
      • 17.5.21 EZKAZ
      • 17.5.22 EZKBA
      • 17.5.23 EZKBB
      • 17.5.24 EZKBC
      • 17.5.25 EZKBD
    • 17.6 Microdiagnostic Flowchart
    • 17.7 Scope Loops
    • 17.8 Nested Scope Loops
    • 17.9 Sample Error Report
    • 17.10 Microdiagnostics Overview
    • 17.11 Device Names/Conventions
    • 17.12 Running the Diagnostics
      • 17.12.1 Diagnostic Notes
      • 17.12.2 Running EVKAA -- Hardcore Instructions Exerciser
      • 17.12.3 Running EVKAB/EVKAC/EVKAE/EVKAX
      • 17.12.4 Running EZCJA/EZXCA/EVCBB
      • 17.12.5 Running DMF32 Standalone Diagnostics
      • 17.12.6 Running EVDWA/EVMBB
      • 17.12.7 Running CIBCI Diagnostics
      • 17.12.8 Running Disk Diagnostics
      • 17.12.9 On-Line Diagnostics
        • 17.12.9.1 DMF32 Diagnostics
        • 17.12.9.2 DEUNA Diagnostics
        • 17.12.9.3 EVAAA Line Printer Diagnostic
        • 17.12.9.4 EVTAA VAX Terminal Diagnostic
        • 17.12.9.5 EVTBA VAX Terminal Exerciser
  • Chapter 18 Remote Services Console (RSC) Setup Procedures
    • 18.1 Introduction
    • 18.2 Remote Services Console (RSC) Overview
    • 18.3 RSC Setup Procedure
      • 18.3.1 Console Communications Software Setup
      • 18.3.2 Console Application Software Setup
      • 18.3.3 VAX/VMS SYSGEN Parameter Setup
      • 18.3.4 Basic Modem Test
  • Chapter 19 Machine Check and Related Information
    • 19.1 Machine Checks
    • 19.2 Machine Check SDF Error Bank
    • 19.3 Initiating a Macrohandler
    • 19.4 Machine Checks/Bug Checks
    • 19.5 Interpreting the Machine Check State
      • 19.5.1 MCSTS
    • 19.6 IBER/CBER
    • 19.7 EBER/NMIFSR
    • 19.8 NMIEAR
    • 19.9 Machine Check vs FRUs
    • 19.10 IBox Failure Matrix
    • 19.11 EBox Failure Matrix
    • 19.12 CBox Failure Matrix
    • 19.13 NMI Failure Matrix
    • 19.14 IBox Errors
    • 19.15 CBox Errors
    • 19.16 EBox Errors
    • 19.17 IBox Parity Error/FRU Cross Reference
    • 19.18 EBox Parity Error/FRU Cross Reference
    • 19.19 CBox Parity Error/FRU Cross Reference
    • 19.20 Machine Specific IPRs
    • 19.21 Handy Routines
    • 19.22 Memory Array Board Stack Probe
    • 19.23 Environmental Problems/Solutions
  • Chapter 20 Removal and Replacement
    • 20.1 Introduction
    • 20.2 Guidelines and Cautions
    • 20.3 Electro-static Discharge Procedures/Module Replacement
    • 20.4 ESD Connections
    • 20.5 Filter Replacement
    • 20.6 876 Power Controller Main Power Circuit Breaker Location
    • 20.7 Air Mover Assembly Replacement
    • 20.8 Air Mover Removal
    • 20.9 Airflow Sensor Replacement
    • 20.10 Airflow Sensor Locations
    • 20.11 Temperature Sensor Replacement
    • 20.12 Temperature Sensor Locations
    • 20.13 Power Regulator Module Replacement
    • 20.14 Power Module Example
    • 20.15 CPU Backplane Replacement
    • 20.16 CPU Backplane Replacement Steps Illustrated
    • 20.17 Memory Backplane Replacement
    • 20.18 Memory Backplane Replacement Steps Illustrated
    • 20.19 VAXBI Backplane (VAXBI-0) Replacement
    • 20.20 VAXBI Backplane (VAXBI-0) Replacement Steps Illustrated
    • 20.21 VAXBI Backplane (VAXBI-1) Replacement
    • 20.22 VAXBI Backplane (VAXBI-1) Replacement Steps Illustrated
    • 20.23 MPS Backplane (MPS 2) Replacement
    • 20.24 MPS Backplane (MPS 2) Removal Steps Illustrated
    • 20.25 MPS Backplane (MPS 1) Replacement
    • 20.26 MPS Backplane (MPS 1) Removal Steps Illustrated
  • Section 7 VAX 8530/8550 Power and Packaging
  • Chapter 21 Power System Components, Block Diagrams, and Flowcharts
    • 21.1 Main System Cabinet -- Front View
    • 21.2 Main System Cabinet -- Rear View
    • 21.3 Power System Simplified Block Diagram
    • 21.4 H405A/H405B UCI Assemblies
    • 21.5 Power System AC Components
    • 21.6 AC Power Distribution
    • 21.7 H405A (Domestic) UCI Schematic
    • 21.8 H405B (Nondomestic) UCI Schematic
    • 21.9 H405A/H405B Rear Panel Connectors
    • 21.10 Stepdown Transformer (Nondomestic Supplies)
    • 21.11 SPC Input/Output Connectors
    • 21.12 SPC Major Outputs
    • 21.13 SPC Internal Backplane Interconnect Diagram
    • 21.14 H7176 PCM Block Diagram
    • 21.15 H7060 CSP Block Diagram
    • 21.16 H7060 CSP Inputs and Outputs
    • 21.17 H7061 ILM Inputs and Outputs
    • 21.18 H7061 ILM Signal Conversions
    • 21.19 MPS Regulator Block Diagram (Typical)
    • 21.20 MPS Regulator Status Indicator
    • 21.21 H7186 Regulator Block Diagram
    • 21.22 H7180 Regulator Block Diagram
    • 21.23 H7189 Regulator Block Diagram
    • 21.24 H7189 Regulator PCB Interconnect Diagram
    • 21.25 Main System Cabling Diagram
    • 21.26 MPS Backplane Connections
    • 21.27 MPS Backplane Interconnect Diagram
    • 21.28 MPS Backplane Connector Locations
    • 21.29 H7188 EMM Front Panel Layout
    • 21.30 EMM Functional Block Diagram
    • 21.31 EMM Module Keying Test Connections
    • 21.32 EMM Module Keying Test Block Diagram
    • 21.33 EMM Voltage Margining Circuit
    • 21.34 EMM AC Lo/DC Lo Circuits
    • 21.35 EMM AC Lo/DC Lo Timing Diagram
    • 21.36 EMM Temperature Sensing Circuit
    • 21.37 EMM Voltage Measuring Circuit
    • 21.38 EMM Voltage Measuring Technique
    • 21.39 EMM Air Flow Sensing Circuit
    • 21.40 Power-Up Flow -- Hardware Initiated Events
    • 21.41 Power-Up Flow -- Console Initiated Events
    • 21.42 Power-Down Flow
  • Chapter 22 Removal and Replacement Procedures
    • 22.1 Introduction
    • 22.2 Guidelines
    • 22.3 Safety Precautions
    • 22.4 Electrostatic Discharge (ESD) Procedures
    • 22.5 System Power Down
    • 22.6 System Power Up
    • 22.7 Replacing a CPU Module
    • 22.8 Replacing a Power Regulator Module
    • 22.9 Replacing a SPC Module
    • 22.10 Replacing the CPU Module
    • 22.11 Replacing the Memory Backplane
    • 22.12 Replacing the MPS Backplane
    • 22.13 Replacing the SPC Backplane
    • 22.14 Replacing the Filters
  • Section 8 MS88-CA Memory Array Module

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