MicroVAX 78032 32-Bit Central Processing Unit User's Guide

Company:Digital Equipment Corporation
Part:EK-78032-UG-PRE
Date:1985-06
Keywords:

Table of Contents

  • Chapter 1 Introduction
    • 1.1 General Description
    • 1.2 Functional Overview
  • Chapter 2 Architecture
    • 2.1 Introduction
    • 2.2 Data Types
      • 2.2.1 Byte
      • 2.2.2 Word
      • 2.2.3 Longword
      • 2.2.4 Quadword
      • 2.2.5 Variable Length Bit Field
      • 2.2.6 Character String
      • 2.2.7 Floating Point
        • 2.2.7.1 F_floating
        • 2.2.7.2 D_floating
        • 2.2.7.3 G_floating
    • 2.3 Registers
      • 2.3.1 Non-Privileged Registers
        • 2.3.1.1 General Registers
        • 2.3.1.2 Processor Status Word
      • 2.3.2 System Registers
        • 2.3.2.1 System Control Block Base Register
        • 2.3.2.2 Process Control Block Base Register
        • 2.3.2.3 Interrupt Registers
        • 2.3.2.4 Memory Management Registers
        • 2.3.2.5 Processor Status Longword
      • 2.3.3 Processor Registers
        • 2.3.3.1 MicroVAX 78032 CPU Specific Registers
          • 2.3.3.1.1 Interval Clock Control and Status Register (ICCS)
          • 2.3.3.1.2 Console Saved Registers (SAVISP, SAVPC, SAVPSL)
    • 2.4 Memory Management
      • 2.4.1 Virtual Address Space
        • 2.4.1.1 Process Space
        • 2.4.1.2 System Space
        • 2.4.1.3 Virtual Address Format
        • 2.4.1.4 Page Protection
      • 2.4.2 Memory Management Control
      • 2.4.3 Access Control
        • 2.4.3.1 Processor Modes
        • 2.4.3.2 Protection Code
        • 2.4.3.3 Length Violation
        • 2.4.3.4 Access Control Violation
        • 2.4.3.5 Access Across A Page Boundary
      • 2.4.4 Address Translation
        • 2.4.4.1 Page Table Entry (PTE)
          • 2.4.4.1.1 Protection Check Before Valid Check
          • 2.4.4.1.2 Changes To Page Table Entries
        • 2.4.4.2 System Space Address Translation
        • 2.4.4.3 Process Space Address Translation
          • 2.4.4.3.1 P0 Region Address Translation
          • 2.4.4.3.2 P1 Region Address Translation
      • 2.4.5 Translation Buffer
        • 2.4.5.1 Translation Buffer Invalidate Single Register
        • 2.4.5.2 Translation Buffer Invalidate All Register
      • 2.4.6 Memory Management Faults
    • 2.5 Exceptions and Interrupts
      • 2.5.1 Processor Interrupt Priority Levels (IPL)
      • 2.5.2 Processor Status
      • 2.5.3 Interrupts
        • 2.5.3.1 Urgent Interrupts -- Levels 18-1F (Hex)
        • 2.5.3.2 Device Interrupts -- Levels 10-17 (Hex)
        • 2.5.3.3 Software Generated Interrupts -- Levels 01-0F (Hex)
        • 2.5.3.4 Interrupt Control
          • 2.5.3.4.1 Software Interrupt Summary Register
          • 2.5.3.4.2 Software Interrupt Request Register
        • 2.5.3.5 Interrupt Priority Level Register
        • 2.5.3.6 Interrupt Example
      • 2.5.4 Exceptions
        • 2.5.4.1 Arithmetic Traps/Faults
          • 2.5.4.1.1 Integer Overflow Trap
          • 2.5.4.1.2 Integer Divide By Zero Trap
          • 2.5.4.1.3 Subscript Range Trap
          • 2.5.4.1.4 Floating Overflow Fault
          • 2.5.4.1.5 Floating Divide By Zero Fault
          • 2.5.4.1.6 Floating Underflow Fault
        • 2.5.4.2 Memory Management Exceptions
          • 2.5.4.2.1 Accesss Control Violation Fault
          • 2.5.4.2.2 Translation Not Valid Fault
        • 2.5.4.3 Operand Reference Exceptions
          • 2.5.4.3.1 Reserved Addressing Mode Fault
          • 2.5.4.3.2 Reserved Operand Exception
        • 2.5.4.4 Instruction Execution Exceptions
          • 2.5.4.4.1 Reserved/Privileged Instruction Fault
          • 2.5.4.4.2 Emulated Instruction Fault
          • 2.5.4.4.3 Extended Function Fault
          • 2.5.4.4.4 Breakpoint Fault
        • 2.5.4.5 Tracing
        • 2.5.4.6 System Failure Exceptions
          • 2.5.4.6.1 Kernel Stack Not Valid Abort
          • 2.5.4.6.2 Interrupt Stack Not Valid Halt
          • 2.5.4.6.3 Machine Check and Memory Read/Write Error Abort
      • 2.5.5 Contrast Between Exceptions and Interrupts
      • 2.5.6 Serialization Of Exceptions and Interrupts
      • 2.5.7 Initiate Exception or Interrupt
      • 2.5.8 System Control Block (SCB)
        • 2.5.8.1 System Control Block Base (SCBB)
        • 2.5.8.2 Vectors
    • 2.6 Process Structure
      • 2.6.1 Process Context
      • 2.6.2 Asynchronous System Traps (AST)
      • 2.6.3 Process Structure Interrupts
    • 2.7 Stacks
      • 2.7.1 Stack Residency
      • 2.7.2 Stack Alignment
      • 2.7.3 Stack Status Bits
      • 2.7.4 Accessing Stack Registers
    • 2.8 Restart Process
      • 2.8.1 Console Entry Protocol
      • 2.8.2 Console Exit Protocol
  • Chapter 3 Instruction Format and Addressing Modes
    • 3.1 Instruction Format
      • 3.1.1 Assembler Radix Notation
      • 3.1.2 Operating Code
      • 3.1.3 Operand Type
    • 3.2 Addressing Modes
      • 3.2.1 General Mode Addressing
        • 3.2.1.1 General Register Address Modes
        • 3.2.1.2 Program Counter Addressing
      • 3.2.2 Branch Addressing
  • Chapter 4 Instruction Set
    • 4.1 Introduction
      • 4.1.1 Instruction Descriptions
      • 4.1.2 Operand Specifier Notation
      • 4.1.3 Operation Description Notation
    • 4.2 Integer Arithmetic and Logical Instructions
    • 4.3 Address Instructions
    • 4.4 Variable Length Bit Field Instructions
    • 4.5 Control Instructions
    • 4.6 Procedure Call Instructions
    • 4.7 Miscellaneous Instructions
    • 4.8 Queue Instructions
      • 4.8.1 Absolute Queues
      • 4.8.2 Self-relative Queues
    • 4.9 Character String Instructions
    • 4.10 Operating System Support Instructions
    • 4.11 Floating Point Instructions
      • 4.11.1 Representation
        • 4.11.1.1 Non-zero Floating Point Numbers
        • 4.11.1.2 Floating Point Zero
        • 4.11.1.3 Reserved Operands
      • 4.11.2 Accuracy
      • 4.11.3 Instruction Descriptions
    • 4.12 Emulated Instructions with Microcode Assist
  • Chapter 5 Bus Transactions
    • 5.1 Introduction
    • 5.2 Bus Cycles
      • 5.2.1 CPU Read Cycle
      • 5.2.2 CPU Write Cycle
      • 5.2.3 Interrupt Acknowledge Cycle
      • 5.2.4 DMA Cycle
    • 5.3 External Processor Cycle
      • 5.3.1 External Processor Read Cycle
      • 5.3.2 External Processor Response Cycle
      • 5.3.3 External Processor Write Cycle
    • 5.4 Memory Access Protocol
    • 5.5 External Processor Protocols
      • 5.5.1 FPU Protocol
      • 5.5.2 Register Protocol
        • 5.5.2.1 Read From Processor Register
        • 5.5.2.2 Write To Processor Register
  • Chapter 6 Pin Description
    • 6.1 Introduction
    • 6.2 Data/Address Bus
    • 6.3 Bus Control
      • 6.3.1 Address Strobe (/AS)
      • 6.3.2 Data Strobe (/DS)
      • 6.3.3 Byte Masks (/BM<3:0>)
      • 6.3.4 Write (/WR)
      • 6.3.5 Data Buffer Enable (/DBE)
      • 6.3.6 Ready (/RDY)
      • 6.3.7 Error (/ERR)
      • 6.3.8 External Processor Strobe (/EPS)
    • 6.4 System Control
      • 6.4.1 Reset (/RESET)
      • 6.4.2 Halt (/HALT)
      • 6.4.3 Control Status (CS<2:0>)
    • 6.5 Interrupt Control
      • 6.5.1 Interrupt Request (/IRQ<3:0>)
      • 6.5.2 Power Fail (/PWRFL)
      • 6.5.3 Interval Timer (/INTTIM)
    • 6.6 DMA Control
      • 6.6.1 DMA Request (/DMR)
      • 6.6.2 DMA Grant (/DMG)
    • 6.7 Supplies
      • 6.7.1 Power (Vdd)
      • 6.7.2 Ground (Vss)
      • 6.7.3 Back Bias Generator (Vbb)
    • 6.8 Clocks
      • 6.8.1 Clock In (CLKI)
      • 6.8.2 Clock Out (CKLO)
    • 6.9 Test (TEST)
    • 6.10 Pin Description Summary
  • Chapter 7 Interfacing
    • 7.1 Introduction
    • 7.2 Power
    • 7.3 Reset/Power-Up
    • 7.4 Halting the Processor
    • 7.5 Memory Subsystem
    • 7.6 Bus Errors
    • 7.7 Interrupts
      • 7.7.1 Powerfail (/PWRFL)
      • 7.7.2 Interval Timer (/INTTIM)
      • 7.7.3 General Interrupts (/IRQ<3:0>)
  • Appendix A DC and AC Characteristics
    • A.1 DC Characteristics
    • A.2 AC Characteristics
      • A.2.1 CLKI Timing
      • A.2.2 CPU Read Cycle, CPU Write Cycle
      • A.2.3 DMA Cycle
      • A.2.4 External Processor Read/Response Enable Cycle, External Processor Write/Command Cycle
      • A.2.5 Reset Timing
  • Appendix B Instruction Set Summary
    • B.1 Introduction
    • B.2 Instruction Summary
    • B.3 Floating Point Instruction Summary
    • B.4 Emulated Instruction with Microcode Assist Summary
  • Appendix C Console Entry and Exit Routines
    • C.1 Introduction
    • C.2 Console Entry and Exit Routine
    • C.3 Memory Management Simulation
  • Appendix D Mechanical Specifications
    • D.1 Packaging

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