DH11 Asynchronous 16-Line Multiplexer Maintenance Manual

Company:Digital Equipment Corporation
Part:EK-0DH11-MM-003
Date:1975-04
Keywords:PDP-11

Table of Contents

  • Chapter 1 General Description
    • 1.1 Introduction
      • 1.1.1 DH11-AA and -AC Line Interfaces
      • 1.1.2 DH11-AB Line Interfaces
      • 1.1.3 DH11-AD and -AE Line Interfaces
    • 1.2 Physical Description
      • 1.2.1 Configurations
      • 1.2.2 Multiplexer Distribution Panel and Power Supply
      • 1.2.3 General Specifications
    • 1.3 Functional Description
      • 1.3.1 Receiver Operation
      • 1.3.2 Silo Operation
      • 1.3.3 Transmitter Operation
      • 1.3.4 Auto-Echo Operation
      • 1.3.5 Interrupts
        • 1.3.5.1 Receiver Interrupts
        • 1.3.5.2 Transmitter Interrupts
  • Chapter 2 Installation
  • Chapter 3 Programming
    • 3.1 Introduction
    • 3.2 Register Bit Assignments
      • 3.2.1 System Control Register
      • 3.2.2 Next Received Character Register
      • 3.2.3 Line Parameter Register
      • 3.2.4 Current Address Register
      • 3.2.5 Byte Count Register
      • 3.2.6 Buffer Active Register
      • 3.2.7 Break Control Register
      • 3.2.8 Silo Status Register
    • 3.3 Operational Features with Programming Significance
      • 3.3.1 Introduction
      • 3.3.2 Floating Device and Vector Addresses
      • 3.3.3 Double-Buffered Receivers and Transmitters
      • 3.3.4 Silo
      • 3.3.5 Zero Baud
      • 3.3.6 Break Signals
      • 3.3.7 Initialize Signal
      • 3.3.8 Maintenance Bits SCR 09 and SSR 15
  • Chapter 4 Detailed Description
    • 4.1 Introduction
    • 4.2 Address Selector and Gating Control
      • 4.2.1 Address Assignment
      • 4.2.2 Device Decoding
      • 4.2.3 Gating Control Logic
      • 4.2.4 Address Response Inhibiting Logic
    • 4.3 Clock Module M4540
      • 4.3.1 Introduction
      • 4.3.2 Counter Functional Descriptions
        • 4.3.2.1 General Information
        • 4.3.2.2 74H74 Flip-Flops
        • 4.3.2.3 7490 Decade Counter
        • 4.3.2.4 7492 Divide by 12 Counter
        • 4.3.2.5 7493 4-Bit Binary Counter
        • 4.3.2.6 74161 Synchronous 4-Bit Counter
      • 4.3.3 Count Down Sequence
    • 4.4 Line Parameter Control Module M7288
      • 4.4.1 Introduction
      • 4.4.2 Signal Buffering
      • 4.4.3 Overall Operation
      • 4.4.4 Transmitter Speed Selection
      • 4.4.5 Receiver Speed Selection
      • 4.4.6 Auto-Echo Enable and Half/Full Duplex Control Signals
    • 4.5 Transmitter Scanner
      • 4.5.1 Introduction
      • 4.5.2 Functional Description
      • 4.5.3 Logic Description
    • 4.6 Current Address Register and Control Logic
      • 4.6.1 Introduction
      • 4.6.2 Current Address Register
        • 4.6.2.1 Functional Description
        • 4.6.2.2 Components
        • 4.6.2.3 Loading the CAR
        • 4.6.2.4 Incrementing the CAR
        • 4.6.2.5 Reading the CAR
      • 4.6.3 CAR Control Logic
        • 4.6.3.1 Loading the CAR
        • 4.6.3.2 Incrementing the CAR
        • 4.6.3.3 Loading the BC Register
      • 4.6.4 High Byte/Low Byte Selection Logic
    • 4.7 Byte Count Register
      • 4.7.1 Introduction
      • 4.7.2 Byte Count Register
        • 4.7.2.1 Functional Description
        • 4.7.2.2 Components
        • 4.7.2.3 Loading and Incrementing the BC Register
        • 4.7.2.4 BC Register Output Logic
    • 4.8 Receiver Scanner
      • 4.8.1 Introduction
      • 4.8.2 Receiver Scanner and Receiver Sequencer
      • 4.8.3 Status Sampling Logic
      • 4.8.4 Auto-Echo Feature
        • 4.8.4.1 Introduction
        • 4.8.4.2 Functional Description
        • 4.8.4.3 Normal Auto-Echo Operation
        • 4.8.4.4 Use of ABANDON Signal to Prevent Auto-Echo Operation
    • 4.9 FIFO Buffer
      • 4.9.1 Introduction
      • 4.9.2 FIFO Buffer Functional Description
      • 4.9.3 FIFO Input Logic
      • 4.9.4 Loading the FIFO (SILO)
      • 4.9.5 Reading the FIFO (SILO)
    • 4.10 System Control Register
      • 4.10.1 General Information
      • 4.10.2 Receiver Interrupt Bits
      • 4.10.3 Transmitter Interrupt Bits
      • 4.10.4 Maintenance Mode
    • 4.11 Half/Full Duplex Control Logic
    • 4.12 Registers and Byte Count Module M7278
      • 4.12.1 Introduction
      • 4.12.2 Unibus Data Line Receivers and Buffers
      • 4.12.3 Line Parameter Register
      • 4.12.4 Buffer Active Register
      • 4.12.5 Break Control Register
      • 4.12.6 Silo Status Register
      • 4.12.7 Output Multiplexer and Unibus Drivers
    • 4.13 M7280 Multiple UART Card
      • 4.13.1 Transmitter Input Data and Data Strobe Signal
      • 4.13.2 Receiver Output Data and Received Data Enable Signal
      • 4.13.3 Reset Data Available Signal
      • 4.13.4 Status Signals
    • 4.14 Bus Transactions Used With the DH11
      • 4.14.1 Introduction
      • 4.14.2 DATI, DATO, and DATOB Transactions (Processor Master)
      • 4.14.3 DATI Transaction With DH11 Master
      • 4.14.4 Interrupt Transaction
  • Chapter 5 Maintenance
    • 5.1 Introduction
    • 5.2 Internal Logic Tests (Part 1)
    • 5.3 On-Line Tests (Part 2)
    • 5.4 General Configuration Information
      • 5.4.1 Introduction
      • 5.4.2 DM11-BB Option
      • 5.4.3 DB11-DC Line Adapters
    • 5.5 Diagnostic Tests Summary
      • 5.5.1 DZDHA DH11 Static Logic Test
      • 5.5.2 DZDHB DH11 Memory Test
      • 5.5.3 DZDHC DH11 Transmitter and Receiver Basic Logic Test
      • 5.5.4 DZDHD DH11 Speed Selection Logic Test
      • 5.5.5 DZDHE DH11 Character Length and Basic Data Test
      • 5.5.6 DZDHF DH11 Single Line Data Test
      • 5.5.7 DZDHG DH11 Multi-Line Data Test
      • 5.5.8 DZDHH DH11 Auto-Echo Tests
      • 5.5.9 DZDHI DH11 Break and Half-Duplex Test
      • 5.5.10 DZDHJ Echo Test
      • 5.5.11 DZDHK DH11-AD Modem Control Test
    • 5.6 Diagnostic Failure Analysis
      • 5.6.1 DZDHA Failures
      • 5.6.2 DZDHB Failures
      • 5.6.3 DZDHC Failures
      • 5.6.4 DZDHD Failures
      • 5.6.5 DZDHE Failures
      • 5.6.6 DZDHF Failures
      • 5.6.7 DZDHG Failures
      • 5.6.8 DZDHH Failures
      • 5.6.9 DZDHI Failures
  • Appendix A Floating Device and Vector Addresses for Communications Devices
    • A.1 Introduction
    • A.2 Device Address
    • A.3 Vector Addresses
  • Appendix B PDP-11 Memory Organization and Addressing Conventions
  • Appendix C Integrated Circuit Descriptions
    • C.1 Introduction
    • C.2 1488 Quad Line Driver
    • C.3 1489 Quad Line Receivers
    • C.4 3341 4-Bit × 64-Word Propagable Register (FI/FO)
    • C.5 4007 Dual-Binary To One-of-Four Line Decoder
    • C.6 4015 Quad Type D Flip-Flop
    • C.7 8266 2-Input 4-Bit Multiplexer
    • C.8 8271 4-Bit Shift Register
    • C.9 Quad 2 Input NOR, 8640
    • C.10 8838 Quad Bus Transceiver
    • C.11 8881 Quad 2 Input NAND Gates
    • C.12 7442 4-Line to 10-Line Decoder
    • C.13 7474/74H74 Dual D-Type Edge-Triggered Flip-Flops
    • C.14 7481 16-Bit Active-Element Memories
    • C.15 7485 4-Bit Magnitude Comparator
    • C.16 7489 64-Bit Read/Write Memory
    • C.17 7490 Decade Counter
    • C.18 7492 Divide by 2 and Divide by 6 Counter
    • C.19 7493 4-Bit Binary Counter
    • C.20 74121 Monostable Multivibrator
    • C.21 74123 Retriggerable Monostable Multivibrator With Clear
    • C.22 74151 8-Line to 1-Line Multiplexer
    • C.23 74154 4-Line to 16-Line Decoder Demultiplexer
    • C.24 74155 Dual 2-Line to 4-Line Decoder
    • C.25 74157 Quad 2-Line to 1-Line Data Selector/Multiplexer
    • C.26 74161 Synchronous 4-Bit Counter
    • C.27 74174 Hex/74175 Quad D-Type Flip-Flops With Clear
    • C.28 74193 Synchronous 4-Bit Up/Down Counter (Dual Clock With Clear)
    • C.29 74197 50 MHz Presettable Decode and Binary Counters/Latches
  • Appendix D Universal Asynchronous Receiver Transmitter (UART)
    • D.1 Introduction
    • D.2 UART Functional Description
  • Appendix E DH11-AD Modem Control Interface
    • E.1 General Description
    • E.2 Functional Description
    • E.3 Physical Description
    • E.4 Environmental Limits, Performance Specifications, and Interface Specifications
    • E.5 Detailed Description
      • E.5.1 Introduction
      • E.5.2 Address Selector Logic
      • E.5.3 Interrupt Control Logic
      • E.5.4 Scan Logic
      • E.5.5 Modem Control (MUX) Logic
      • E.5.6 Maintenance Mode
    • E.6 Operational Programming
      • E.6.1 Control Status Register (CSR) (Address: 770XX0)
      • E.6.2 Line Status Register (LSR) (Address: 770XX2)
      • E.6.3 System Addresses
      • E.6.4 Interrupt Vectors
      • E.6.5 Timing Considerations
    • E.7 Maintenance
      • E.7.1 Introduction
      • E.7.2 Testing Configurations
        • E.7.2.1 Off Line
        • E.7.2.2 On Line
  • Appendix F Modem Timing and Flow Diagrams

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