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| version 2.0.7 |
| Part | Date | Title | Status |
|---|---|---|---|
| 292027-001 | AP-304 Simulation of EPLD Timing | ||
| 292030-001 | AP-307 EPLD's, PLAS and TTL Comparing the "Hidden Costs" in Production | ||
| 292031-001 | A typical Latch/Register Construction in EPLDs (Application Brief) | ||
| 292032-001 | AP-305 Dual Port Memory Control Using the 5CBIC | ||
| 292034-001 | AB-17 Configuring the 5CBIC for Your Design | ||
| 292035-001 | AP-308 The Multiplexed Bus Interface with the 5CBIC | ||
| 292036-001 | AP-309 DRAM Address Interface with the 5CBIC | ||
| 292038-001 | AP-310 High Performance Driver for 82510 | ||
| 292039-001 | AP-311 Using Macros in EPLD Designs | ||
| 292040-001 | AP-312 Creating Macros for EPLD Designs |
